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DS2196L Datasheet(PDF) 6 Page - Dallas Semiconductor |
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DS2196L Datasheet(HTML) 6 Page - Dallas Semiconductor |
6 / 157 page DS2196 6 of 157 1. INTRODUCTION The DS2196 is a derivative of the DS21352 T1 SCT. The feature set has been optimized for transport applications commonly found in T1 transmission equipment. The DS2196 register map and register bit definitions are compatible with the DS21352/DS21552, allowing for easy migration to the DS2196. Interface designs requiring per-channel code insertion, elastic stores, and ANSI 1’s density monitoring should use the DS21352 or DS21552. 1.1 Feature Highlights § Main features – Two full-featured independent framers – Short/long haul LIU – 100-pin LQFP small package – 3.3V operation with 5V tolerant I/O § 8-bit parallel control port – Multiplexed or nonmultiplexed buses – Intel or Motorola formats – Polled or interrupt environments § HDLC Support – Two independent HDLC controllers – 64-byte Rx and Tx buffers – Access FDL or single/multiple DS0 channels § ANSI T1.403-1998 support – NPRMs – SPRMs – RAI-CI detection and generation – AIS-CI detection and generation § Format Conversion – D4 to ESF framing – ESF to D4 framing § LIU – Long and short-haul support – Receive sensitivity: 0dB to -36dB – 32-bit or 128-bit crystal-less jitter attenuator – DSX-1 and CSU line buildout options – Provisions for custom waveform generation § DS1 Idle Code Generation – User-defined – Fixed 7F Hex – Digital milliwatt § In-band repeating pattern generator and detector – Programmable pattern generator – Three programmable pattern detectors – Patterns from 1 to 8 bits or 16 bits in length § Programmable on-chip bit error-rate testing – Pseudorandom patterns including QRSS – User-defined repetitive patterns – Daly pattern – Error insertion – Bit and error counts § Payload Error Insertion – Error insertion in the payload portion of the T1 frame in the transmit path – Errors can be inserted over the entire frame or selected channels – Insertion options include continuous and absolute number with selectable insertion rates § Function Isolation – All key signals are routed to pins – LIU, Framer A, and Framer B can be disconnected from each other § Supports both NRZ and bipolar interfaces § F-bit corruption for line testing § Programmable output clocks for Fractional T1 § Fully independent transmit and receive functionality in each framer § Large path and line error counters including BPV, CV, CRC6, and framing bit errors § Ability to calculate and check CRC6 according to the Japanese standard § Ability to generate Yellow Alarm according to the Japanese standard § Per channel loopback § RCL, RLOS, RRA, and RAIS alarms interrupt on change of state § Hardware pins to indicate receive loss-of- sync and receive bipolar violations § IEEE 1149.1 JTAG Boundary Scan |
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