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ICS889834AK Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS889834AK Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 7 page www.icst.com/products/hiperclocks.html Aug 02, 2002 4 Integrated Circuit Systems, Inc. HiPerClockS™ Application Note 3.3V LVPECL DRIVER TERMINATION AC Coupled Termination For AC termination, the offset level needs to be taken care of after the AC capacitors. A bias circuit might be required. The board design engineer needs to verify what type of receiver is being driven. A few examples of AC couple termination are shown in this section. In Figure 6, the R3 and R4 at the driver pins provide a current path for the LVPECL driver. R1 and R2 serve as matched load termination. The power supply V BB controls the offset level so that the signal offset fall within the VCMR input requirement of the receiver. Figure 7 and Figure 8 are equivalent to Figure 5. The Figure 7 is equivalent to V BB=VCC-2V. This offset is suitable for interfacing with HiPerClockS TM CLK/nCLK input. Figure 8 is equivalent to V BB=VCC-1.3V. This offset is suitable for interfacing with HiPerClockS TM PCLK/nPCLK input. Figure 9 shows AC termination with the offset bias voltage V BB provided at the receiving end. Figure 10 shows AC termination with the offset bias voltage V BB provided by the receiver device. In some cases, for the receiver with built-in bias resistors R1 and R2, the termination is shown in Figure 11. R3 100-180 C2 nTL1 Zo = 50 Td + - VCCO=3.3V R4 100-180 VBB R2 50 C1 TL1 Zo = 50 Td R1 50 3v3 PECL Driver U1 Figure 6 AC Coupled with V BB power supply provided at the receiving end |
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