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MAX32626IWY+T Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX32626IWY+T Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 27 page (Internal bandgap reference selected and ADC_SCALE = ADC_REFSCL = 1 unless otherwise specified. Specifications marked GBD are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Resolution 10 Bits ADC Clock Rate fADC_CLK 0.1 8 MHz ADC Clock Period tADC_CLK 1/fADC_ CLK μs Input Voltage Range VAIN AIN0-AIN3, ADC_CHSEL = 0–3, BUF_BYPASS = 0 0.05 VDD18 V AIN0–AIN1, ADC_CHSEL = 4–5, BUF_BYPASS = 0 0.05 5.5 AIN0–AIN3, ADC_CHSEL = 0–3, BUF_BYPASS = 1 VSS VDD18 AIN0-AIN1, ADC_CHSEL = 4-5, BUF_BYPASS = 1 VSS 5.5 Input Dynamic Current, Switched Capacitance IAIN ADC active, ADC buffer bypassed 4.5 μA ADC active, ADC buffer enabled 50 nA Analog Input Capacitance CAIN Fixed capacitance to VSS 1 pF Dynamically switched capacitance 250 nF Integral Nonlinearity INL ±2 LSB Differential Nonlinearity DNL ±1 LSB Offset Error VOS ±1 LSB Gain Error GE ±2 LSB Signal-to-Noise Ratio SNR 58.5 dB Signal-to-Noise and Distortion SINAD 58.5 dB Total Harmonic Distortion THD -68.5 dB Spurious Free Dynamic Range SFDR 74 dB ADC Active Current IADC ADC active, reference buffer enabled, input buffer disabled 240 µA Input Buffer Active Current IINBUF 53 μA ADC Setup Time tADC_SU Any power-up of ADC clock, ADC bias, reference buffer or input buffer, to CpuAdcStart 10 µs Any power-up of ADC clock or ADC bias to CpuAdcStart 48 tACLK ADC Output Latency tADC 1025 tACLK ADC Sample Rate fADC 7.8 ksps ADC Input Leakage IADC_LEAK AIN0 or AIN1, ADC inactive or channel not selected 0.12 4 nA AIN2 or AIN3, ADC inactive or channel not selected 0.02 1 Electrical Characteristics - ADC MAX32625/MAX32626 Ultra-Low Power, High-Performance ARM Cortex-M4F Microcontroller for Wearables www.maximintegrated.com Maxim Integrated │ 10 |
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