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THC63LVD1023B Datasheet(PDF) 3 Page - California Eastern Labs |
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THC63LVD1023B Datasheet(HTML) 3 Page - California Eastern Labs |
3 / 26 page THC63LVD1023B_Rev.3.0_E Copyright©2011 THine Electronics, Inc. 3/26 THine Electronics, Inc. Pin Description Pin Name Pin # Type Description ASYNC=L ASYNC=H TA1+, TA1- 70, 71 LVDS OUT The 1st Link. The 1st pixel output data when Dual-Link. TB1+, TB1- 68, 69 TC1+, TC1- 64, 65 TD1+, TD1- 58, 59 TE1+, TE1- 56, 57 TCLK1+, TCLK1- 62, 63 LVDS Clock Out for 1st and 2nd Link. TA2+, TA2- 52, 53 The 2nd Link. These pins are disabled when Single Link. TB2+, TB2- 50, 51 TC2+, TC2- 46, 47 TD2+, TD2- 40, 41 TE2+, TE2- 38, 39 TCLK2+, TCLK2- 44, 45 See following table. Case1: LVDS Clock out for 2nd link. Case2: LVDS Clock out for 1st link. Case3: Additional LVDS Clock out. Identical to TCLK1+/- Case4: Not available (High-Impedance) R19 ~ R10 TB12~TB10, TA16~TA10 87 - 84, 81 - 76 IN ASYNC=L The 1st Pixel Data Inputs. ASYNC=H Data Inputs. G19 ~ G10 TC15~TC10, TB16~TB13 99 - 95, 92 - 88 B19 ~ B10 TE11~TE10, TD16~TD10, TC16 112 -110, 108 -106, 103 - 100 R29 ~ R20 TA24~TA20, TE16~TE12 124 - 115 IN ASYNC=L The 2nd Pixel Data Inputs. ASYNC=H Data Inputs. G29 ~ G20 TC20, TB26~TB20, TA26~TA25 136 - 127 B29 ~ B20 TD23~TD20, TC26~TC21 6, 5, 2, 1, 144 - 139 ASYNC MODE0 MODE1 MODE2 Description Hx x L Case1 Hx x H Case2 LL x x Case3 LH L x Case4 LH H L Case4 LH H H Case3 |
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