7

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Note 7: Two diodes clamp the OS analog inputs to

impedance of the sensor, prevents damage to the LM9810/20 from transients during power-up.

Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin.

Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: Integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the

ADC.

LM9810/20 can correct for using its internal PGA.

Note 13:

PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula

where

.

Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, and a single OS input with a gain register setting of 1 (000001b) and an offset

register setting of 0 (000000b).

The current required to switch the digital data bus can be calculated from: Isw = 2*Nd*Psw*CL*

of each data bit switching, CL is the capacitive loading on each data pin,

6, Psw should be .5, and

ital output pin (

will be drawn through the

OS Input

AGND

VA

TO INTERNAL

CIRCUITRY

CCD Output Signal

Gain

PGA

V

V

----





G

0

X

PGA code

32

---------------------------

+

=X

G

31

G

0

–

()32

31

------

=