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TPS7B6333-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS7B6333-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 30 page 6 TPS7B6333-Q1, TPS7B6350-Q1 SLVSDU9 – FEBRUARY 2017 www.ti.com Product Folder Links: TPS7B6333-Q1 TPS7B6350-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) This test is done with VOUT in regulation, measuring the VIN – VOUT when VOUT drops by 100 mV from the rated output voltage at the specified load. (2) Design Information – Not tested, determined by characterization. 6.5 Electrical Characteristics VIN = 14 V, COUT ≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, TJ = –40°C to 150°C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND CURRENT (IN) VIN Input voltage 4 40 V I(SLEEP) Input sleep current EN = OFF 4 µA I(Q) Input quiescent current VIN = 5.6 V to 40 V for fixed 5-V VOUT; VIN = 4 V to 40 V for fixed 3.3‑V VOUT; EN = ON; watchdog disabled; IOUT < 1 mA; TJ < 80°C 19 29.6 µA VIN = 5.6 V to 40 V for fixed 5-V VOUT; VIN = 4 V to 40 V for fixed 3.3‑V VOUT; EN = ON; watchdog enabled; IOUT < 1 mA 28 42 VIN = 5.6 V to 40 V for fixed 5-V VOUT; VIN = 4 V to 40 V for fixed 3.3‑V VOUT; EN = ON; watchdog enabled; IOUT < 100 mA 78 98 V(UVLO) Undervoltage lockout, falling Ramp VIN down until output is turned off 2.6 V V(UVLO_HYST) UVLO hysteresis 0.5 V ENABLE INPUT, WATCHDOG TYPE SELECTION AND FSEL (EN, WTS, AND FSEL) VIL Low-level input voltage 0.7 V VIH High-level input voltage 2 V Vhys Hysteresis 150 mV WATCHDOG ENABLE (WD_EN PIN) VIL Low-level input threshold voltage for watchdog enable pin Watchdog enabled 0.7 V VIH High-level input threshold voltage for watchdog enable pin Watchdog disabled 2 V IWD_EN Pulldown current for watchdog enable pin VWD_EN = 5 V 3 µA REGULATED OUTPUT (OUT) VOUT Regulated output VIN = 5.6 V to 40 V for fixed 5-V VOUT; VIN = 4 V to 40 V for fixed 3.3‑V VOUT; IOUT = 0 to 300 mA –2% 2% ΔVOUT(ΔVIN) Line regulation VIN = 5.6 V to 40 V 10 mV ΔVOUT(ΔIOUT) Load regulation IOUT = 1 mA to 300 mA 20 mV V(dropout) Dropout voltage (VIN – VOUT) IOUT = 300 mA (1) 300 400 mV IOUT = 200 mA (1) 170 260 IOUT Output current VOUT in regulation 0 300 mA I(LIM) Output current limit VOUT shorted to ground, VIN = 5.6 V to 40 V 301 680 1000 mA PSRR Power supply ripple rejection(2) IOUT = 100 mA; COUT = 10 µF; frequency (f) = 100 Hz 60 dB IOUT = 100 mA; COUT = 10 µF; frequency (f) = 100 kHz 40 POWER GOOD (PG, PGADJ) VOL(PG) PG output, low voltage IOL = 5 mA, PG pulled low 0.4 V Ilkg(PG) PG pin leakage current PG pulled to VOUT through a 10‑kΩ resistor 1 µA V(PG_TH) Default power-good threshold VOUT powered above the internally set tolerance, PGADJ pin shorted to ground 89.6 91.6 93.6 % of VOUT V(PG_HYST) Power-good hysteresis VOUT falling below the internally set tolerance hysteresis 2 % of VOUT |
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