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AD5426YRM-REEL Datasheet(PDF) 4 Page - Analog Devices

Part # AD5426YRM-REEL
Description  8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5426YRM-REEL Datasheet(HTML) 4 Page - Analog Devices

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REV. 0
–4–
AD5426/AD5432/AD5443
TIMING CHARACTERISTICS1
Parameter
3.0 V to 5.5 V
4.5 V to 5.5 V
Unit
Conditions/Comments
fSCLK
50
50
MHz max
Max clock frequency
t1
20
20
ns min
SCLK cycle time
t2
88
ns min
SCLK high time
t3
88
ns min
SCLK low time
t4
2
13
13
ns min
SYNC falling edge to SCLK active edge setup time
t5
55
ns min
Data setup time
t6
33
ns min
Data hold time
t7
55
ns min
SYNC rising edge to SCLK active edge
t8
30
30
ns min
Minimum
SYNC high time
t9
3
80
45
ns typ
SCLK active edge to SDO valid
120
65
ns max
NOTES
1See Figures 1 and 2. Temperature range is as follows: Y version: –40
°C to +125°C. Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2.
2Falling or rising edge as determined by control bits of serial word.
3Daisy-chain and readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3.
Specifications subject to change without notice.
(VDD = 3 V to 5.5 V, VREF = 10 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted.)
DB15
DB0
t4
t8
t5
t6
t2
t3
t1
t7
SCLK
SYNC
DIN
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 1. Standalone Mode Timing Diagram
DB15 (N)
DB0 (N)
DB15
(N+1)
DB0 (N+1)
SCLK
SYNC
SDIN
SDO
ALTERNATiVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
t4
t5
t6
t2
t1
t3
t7
t8
t9
DB15(N)
DB0(N)
Figure 2. Daisy-chain and Readback Modes Timing Diagram


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