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AM29LV800T-90R Datasheet(PDF) 10 Page - Advanced Micro Devices |
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AM29LV800T-90R Datasheet(HTML) 10 Page - Advanced Micro Devices |
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10 / 48 page  10 Am29LV800T/Am29LV800B PRELIMINARY USER BUS OPERATIONS Read Mode The Am29LV800 has three control functions which must be satisfied in order to obtain data at the outputs: s CE is the power control and should be used for device selection (CE = VIL) s OE is the output control and should be used to gate data to the output pins if the device is selected (OE = VIL) s WE remains at VIH Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The out- put enable access time (tOE) is the delay from the fall- ing edge of OE to valid data at the output pins (assuming the addresses have been stable at least tACC – tOE time). Standby Mode The Am29LV800 is designed to accommodate two modes for low standby power consumption. Both modes are enabled by applying the voltages specified below to the CE and RESET pins. These modes are available for either TTL/NMOS or CMOS logic level de- signs. The first mode, ICC3 for TTL/NMOS compatible I/ Os (current consumption <1 mA max.), is enabled by applying a TTL logic level ‘1’ (VIH) to the CE control pin with RESET = VIH. ICC3 for CMOS compatible I/Os (current consumption <5 µA max.), is enabled when a CMOS logic level ‘1’ (VCC ± 0.3 V) is applied to the CE control pin with RESET = VCC ± 0.3 V. While in the ICC3 standby mode, the data I/O pins remain in the high im- pedance state independent of the voltage level applied to the OE input. See the DC Characteristics section for more details on Standby Modes. Deselecting CE (CE = VIH or VCC ± 0.3 V, with RESET = VIH or VCC ± 0.3 V), will put the device into the ICC3 standby mode. If the device is deselected during an Embedded Algorithm™ operation, it will continue to draw active power (ICC2), prior to entering the standby mode, until the operation is complete. Subsequent reselection of the device for active operations (CE = VIL) will commence pursuant to the AC timing specifications. Automatic Sleep Mode Advanced power management features such as the automatic sleep mode minimize Flash device energy consumption. This is extremely impor tant in battery-powered applications. The Am29LV800 auto- matically enables the low-power, automatic sleep mode when addresses remain stable for 200 ns. Auto- matic sleep mode is independent of the CE, WE, and OE control signals. Typical sleep mode current draw is 200 nA (for CMOS-compatible operation). Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Output Disable If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. |
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