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C8051F54X Datasheet(PDF) 52 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 52 Page - Silicon Laboratories |
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52 / 276 page  C8051F54x 52 Rev. 1.1 Table 6.4. Reset Electrical Characteristics –40 to +125 °C unless otherwise specified. Parameter Conditions Min Typ Max Units RST Output Low Voltage VIO = 5 V; IOL = 70 µA — — 40 mV RST Input High Voltage 0.7 x VIO — — RST Input Low Voltage — — 0.3 x VIO RST Input Pullup Current RST = 0.0 V, VIO = 5 V — 49 115 µA VDD RST Threshold (VRST-LOW) 1.65 1.75 1.80 V VDD RST Threshold (VRST-HIGH) 2.25 2.30 2.45 V Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation VDD = 2.1 V VDD = 2.5 V 200 200 340 250 600 600 µs Reset Time Delay Delay between release of any reset source and code execution at location 0x0000 — 155 175 µs Minimum RST Low Time to Generate a System Reset 6 — — µs VDD Monitor Turn-on Time — 60 100 µs VDD Monitor Supply Current — 1 2 µA Table 6.5. Flash Electrical Characteristics VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. Parameter Conditions Min Typ Max Units Flash Size C8051F540/1/2/3 163841 Bytes C8051F544/5/6/7 8192 Endurance 20 k 150 k — Erase/Write Retention 125 °C 10 — — Years Erase Cycle Time 25 MHz System Clock 28 30 45 ms Write Cycle Time 25 MHz System Clock 79 84 125 µs VDD Write/Erase Operations VRST-HIGH 2 — — V 1. On the 16 kB Flash devices, 1024 bytes at addresses 0x3C00 to 0x3FFF are reserved. 2. See Table 6.4 for the VRST-HIGH specification. |
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