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C8051F54X Datasheet(PDF) 73 Page - Silicon Laboratories

Part # C8051F54X
Description  Mixed Signal ISP Flash MCU Family
Download  276 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F54X Datasheet(HTML) 73 Page - Silicon Laboratories

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C8051F54x
Rev. 1.1
72
9. Voltage Regulator (REG0)
C8051F54x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at the
VREGIN pin can be as high as 5.25 V. The output can be selected by software to 2.1 V or 2.6 V. When
enabled, the output of REG0 appears on the VDD pin, powers the microcontroller core, and can be used to
power external devices. On reset, REG0 is enabled and can be disabled by software.
The Voltage regulator can generate an interrupt (if enabled by EREG0, EIE2.0) that is triggered whenever
the VREGIN input voltage drops below the dropout threshold voltage. This dropout interrupt has no pending
flag and the recommended procedure to use it is as follows:
1. Wait enough time to ensure the VREGIN input voltage is stable
2. Enable the dropout interrupt (EREG0, EIE2.0) and select the proper priority (PREG0, EIP2.0)
3. If triggered, inside the interrupt disable it (clear EREG0, EIE2.0), execute all procedures necessary to
protect your application (put it in a safe mode and leave the interrupt now disabled).
4. In the main application, now running in the safe mode, regularly check the DROPOUT bit (REG0CN.0).
Once it is cleared by the regulator hardware, the application can enable the interrupt again (EREG0,
EIE1.6) and return to the normal mode operation.
The input (VREGIN) and output (VDD) of the voltage regulator should both be bypassed with a large capaci-
tor (4.7 µF + 0.1 µF) to ground as shown in Figure 9.1 below. This capacitor will eliminate power spikes
and provide any immediate power required by the microcontroller. The settling time associated with the
voltage regulator is shown in Table 6.8 on page 54.
Figure 9.1. External Capacitors for Voltage Regulator Input/Output—
Regulator Enabled
If the internal voltage regulator is not used, the VREGIN input should be tied to VDD, as shown in Figure 9.2.
VDD
VDD
REG0
4.7 µF
4.7 µF
.1 µF
.1 µF
VREGIN


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