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C8051F54X Datasheet(PDF) 93 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 93 Page - Silicon Laboratories |
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93 / 276 page  C8051F54x 92 Rev. 1.1 Figure 12.3. SFR Page Stack After SPI0 Interrupt Occurs While in the SPI0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the SPI0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that was in the SFRPAGE register before the PCA interrupt (SFR Page 0x00 for SPI00) is pushed down the stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in this case SFR Page 0x0F for SMB0ADR) is pushed down to the SFRLAST register, the “bottom” of the stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be overwritten. See Figure 12.4. 0x00 (SPI0) 0x0F (SMB0ADR) SFRPAGE SFRLAST SFRNEXT SFRPAGE pushed to SFRNEXT SFR Page 0x00 Automatically pushed on stack in SFRPAGE on SPI0 interrupt |
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