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C8051F54X Datasheet(PDF) 16 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 16 Page - Silicon Laboratories |
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16 / 276 page  C8051F54x Rev. 1.1 16 2. Ordering Information The following features are common to all devices in this family: 50 MHz system clock and 50 MIPS throughput (peak) 1280 bytes of RAM (256 internal bytes and 1024 XRAM bytes) Internal 24 MHz oscillator SMBus / I2C, Enhanced SPI, Enhanced UART Four Timers Six Programmable Counter Array channels Internal Voltage Regulator 12-bit, 200 ksps ADC, Internal Voltage Reference and Temperature Sensor Two Analog Comparators Table 2.1 shows the features that differentiate the devices in this family. |
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