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C8051F54X Datasheet(PDF) 26 Page - Silicon Laboratories

Part # C8051F54X
Description  Mixed Signal ISP Flash MCU Family
Download  276 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F54X Datasheet(HTML) 26 Page - Silicon Laboratories

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C8051F54x
26
Rev. 1.1
Figure 4.4. QFN-32 Landing Diagram
Table 4.4. QFN-32 Landing Diagram Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
4.80
4.90
X2
3.20
3.40
C2
4.80
4.90
Y1
0.75
0.85
e
0.50 BSC
Y2
3.20
3.40
X1
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60
μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 3x3 array of 1.0 mm openings on a 1.20 mm pitch should be used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.


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