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MB85RC04VPNF-G-JNE1 Datasheet(PDF) 2 Page - Fujitsu Component Limited. |
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MB85RC04VPNF-G-JNE1 Datasheet(HTML) 2 Page - Fujitsu Component Limited. |
2 / 29 page MB85RC04V 2 DS501-00016-2v0-E ■ PIN ASSIGNMENT ■ PIN FUNCTIONAL DESCRIPTIONS Pin Number Pin Name Functional Description 1NC No Connect pin Leave this pin open, or connect to VDD or VSS. 2, 3 A1, A2 Device Address pins The MB85RC04V can be connected to the same data bus up to 4 devices. Device addresses are used in order to identify each of these devices. Connect these pins to VDD pin or VSS pin externally. Only if the combination of VDD and VSS pins matches Device Address Code inputted from the SDA pin, the device operates. In the open pin state, A1 and A2 pins are internally pulled-down and recognized as the "L" level. 4 VSS Ground pin 5SDA Serial Data I/O pin This is an I/O pin which performs bidirectional communication for both memory address and writing/reading data. It is possible to connect multiple devices. It is an open drain output, so a pull-up resistor is required to be connected to the ex- ternal circuit. 6SCL Serial Clock pin This is a clock input pin for input/output timing serial data. Data is sampled on the rising edge of the clock and output on the falling edge. 7WP Write Protect pin When the Write Protect pin is the “H” level, the writing operation is disabled. When the Write Protect pin is the “L” level, the entire memory region can be overwritten. The reading operation is always enabled regardless of the Write Protect pin input level. The write protect pin is internally pulled down to VSS pin, and that is recognized as the “L” level (write enabled) when the pin is the open state. 8 VDD Supply Voltage pin VSS SDA A1 VDD SCL A2 NC WP 8 7 6 5 4 3 2 1 (TOP VIEW) (FPT-8P-M02) |
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