MB85RC256V

DS501-00017-3v0-E

5

■ ACKNOWLEDGE (ACK)

signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually

outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully transmitted and

received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow

the acknowledge signal to be received and checked. During this Hi-Z released period, the receiver side pulls

the SDA line down to indicate the “L” level that the previous 8 bits communication is successfully received.

In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side

stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state

after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition

in this released bus state.

• Acknowledge timing overview diagram

SCL

123

8

9

SDA

Start

ACK

The transmitter side should always release SDA on the

9th bit. At this time, the receiver side outputs a pull-down

if the previous 8 bits data are received correctly (ACK re-

sponse).