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MB85RS2MTPH-G Datasheet(PDF) 1 Page - Fujitsu Component Limited. |
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MB85RS2MTPH-G Datasheet(HTML) 1 Page - Fujitsu Component Limited. |
1 / 26 page FUJITSU SEMICONDUCTOR DATA SHEET Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.3 Memory FRAM 2 M (256 K × 8) Bit SPI MB85RS2MT ■ DESCRIPTION MB85RS2MT is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 262,144 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS2MT adopts the Serial Peripheral Interface (SPI). The MB85RS2MT is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85RS2MT can be used for 1013 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS2MT does not take long time to write data like Flash memories or E2PROM, and MB85RS2MT takes no wait time. ■ FEATURES • Bit configuration : 262,144 words × 8 bits • Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) • Operating frequency : 25 MHz (Max) For FSTRD command 2.7 V to 3.6 V, 40 MHz (Max) • High endurance : 1013 times / byte • Data retention : 10 years (+85 °C) • Operating power supply voltage : 1.8 V to 3.6 V • Low power consumption : Operating power supply current 10.6 mA (Max@25 MHz) (TBD) Standby current 150 μA (Max) (TBD) Sleep current 10 μA (Max) (TBD) • Operation ambient temperature range : -40 °C to +85 °C • Package : 8-pin plastic SOP (FPT-8P-M08) 8-pin plastic DIP (DIP-8P-M03) RoHS compliant DS501-00023-0v01-E |
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