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FEATURES

DESCRIPTION

APPLICATIONS

PIN ASSIGNMENTS

AI

AO

BO

CO

DO

AI

AI

BI

BI

C1

C1

D1

D1

D1

E2

E1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AI

AI

AO

E1

BO

BI

BI

GND

VCC

DI

DI

DO

E2

CO

CI

CI

D PACKAGE

(TOP VIEW)

ENABLE TRUTH TABLE

TB5R1, TB5R2

SLLS588B – NOVEMBER 2003 – REVISED MAY 2004

QUAD DIFFERENTIAL PECL RECEIVERS

•

Functional Replacements for the Agere

These quad differential receivers accept digital data

BRF1A, BRF2A, BRS2A, and BRS2B

over balanced transmission lines. They translate

differential input logic levels to TTL output logic

•

Pin Equivalent to General Trade 26LS32

levels.

•

High Input Impedance Approximately 8 k

Ω

The TB5R1 is a pin- and function-compatible replace-

•

4-ns Maximum Propagation Delay

ment for the Agere systems BRF1A and BRF2A; it

•

TB5R1 Provides 50-mV Hysteresis

includes 3-kV HBM and 2-kV CDM ESD protection.

•

TB5R2 With -125-mV Threshold Offset for

The TB5R2 is a pin- and function-compatible replace-

Preferred State Output

ment for the Agere systems BRS2A and BRS2B and

•

-1.1-V to 7.1-V Common Mode Range

incorporates a 125-mV receiver input offset, preferred

state output, 3-kV HBM and 2-kV CDM ESD protec-

•

Single 5-V

±10% Supply

tion. The TB5R2 preferred state feature places the

•

Slew Rate Limited (1 ns min 80% to 20%)

high state when the inputs are open, shorted to

•

TB5R2 Output Defaults to Logic 1 When In-

ground, or shorted to the power supply.

The power-down loading characteristics of the re-

•

ESD Protection HBM > 3 kV, CDM > 2 kV

ceiver input circuit are approximately 8 k

Ω relative to

•

Operating Temperature Range: -40

°C to 85°C

the power supplies; hence they do not load the

transmission line when the circuit is powered down.

•

Available in Gull-Wing SOIC (JEDEC MS-013,

DW) and SOIC (D) Package

The packaging for these differential line receivers

include a 16-pin gull wing SOIC (DW) and SOIC (D).

The enable inputs of this device include internal

•

Digital Data or Clock Transmission Over Bal-

pullup resistors of approximately 40 k

Ω that are

anced Lines

if the inputs are open circuited.

FUNCTIONAL BLOCK DIAGRAM

E1

E2

CONDITION

0

0

Active

1

0

Active

0

1

Disabled

1

1

Active

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2003–2004, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.