THS14F01, THS14F03

14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS

WITH FIFO INTERNAL REFERENCE AND PGA

SLAS285 – JUNE 2000

7

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

The parallel interface of the THS14F01/3 ADC features 3-state buffers making it possible to directly connect

it to a data bus. The output buffers are enabled by driving the OE input low.

Besides the sample results, it is also possible to read back the values of the control register, the PGA register,

and the control register. Which register is read is determined by the address inputs A[1,0]. The ADC results are

available at address 0.

The timing of the control signals is described in the following sections.

The FIFO can be disabled by setting FC to 0 (FIFO reset, default at power on). This makes it possible to access

the device synchronously.

In this case the data is updated on every clock cycle.

S9

S10

S11

S12

CLK

D[13:0]

OV

Analog

Input

C1

C2

C3

tw(CLK)

tw(CLK)

td

OE

C0

CS

A[1:0]

X

X

ten

tsu(OE-ACS)

tdis

th(CS)

th(A)

Figure 2. Sample Timing