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W6811 Datasheet(PDF) 7 Page - Winbond |
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W6811 Datasheet(HTML) 7 Page - Winbond |
7 / 37 page W6811 Publication Release Date: October 23, 2003 - 7 - Revision A10 6. PIN DESCRIPTION Pin Name Pin No. VDD * Functionality VREF 1 A This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be decoupled to VSSA through a 0.1 µF ceramic decoupling capacitor. No external loads should be tied to this pin. RO- 2 A Inverting output of the receive smoothing filter. This pin can typically drive a 2 k Ω load to 1.575 volt peak referenced to the analog ground level. PAI 3 A This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage. PAO- 4 A Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced to the VAG voltage level. PAO+ 5 A Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 Volt peak referenced to the VAG voltage level. VDDA 6 A Analog power supply. This pin should be decoupled to VSSA with a 0.1µF ceramic capacitor. NC 7 Not Connected VDDD 8 D Digital power supply. This pin should be decoupled to VSSD with a 0.1µF ceramic capacitor. For correct operation, VDDD value should always be lower then VDDA. FSR 9 D 8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit and receive are synchronous operations. PCMR 10 D PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins. BCLKR 11 D PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is selected when this pin is tied to VSSD. The IDL mode is selected when this pin is tied to VDDD. This pin can also be tied to the BCLKT when transmit and receive are synchronous operations. PUI 12 D Power up input signal. When this pin is tied to VDDD, the part is powered up. When tied to VSSD, the part is powered down. MCLK 13 D System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the case of 256 and 512 kHz frequency. BCLKT 14 D PCM transmit bit clock input pin. PCMT 15 D PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins. FST 16 D 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. |
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