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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC8T245-EP

SCES770A – DECEMBER 2008 – REVISED MARCH 2017

SN74LVC8T245-EP 8-Bit Dual-Supply Bus Transceiver With

Configurable Voltage Translation and Tri-State Outputs

1

(1)

Additional temperature ranges are available – contact factory.

1 Features

1

•

•

GND, All Are in the High-Impedance State

•

Fully Configurable Dual-Rail Design Allows Each

Port to Operate Over the Full 1.65-V to 5.5-V

Power-Supply Range

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

–

4000-V Human-Body Model (A114-A)

–

200-V Machine Model (A115-A)

–

1000-V Charged-Device Model (C101)

2 Applications

•

Controlled Baseline

•

One Assembly/Test Site

•

One Fabrication Site

•

Available in Military (–55°C/125°C) Temperature

•

Extended Product Life Cycle

•

Extended Product-Change Notification

•

Product Traceability

3 Description

This 8-bit noninverting bus transceiver uses two

separate

configurable

power-supply

rails.

The

voltage from 1.65 V to 5.5 V. The B port is designed

1.65 V to 5.5 V. This allows for universal low-voltage

bidirectional translation between any of the 1.8-V,

2.5-V, 3.3-V, and 5.5-V voltage nodes.

The

SN74LVC8T245-EP

is

designed

for

asynchronous

communication

between

two

data

buses. The logic levels of the direction-control (DIR)

input and the output-enable (OE) input activate either

the B-port outputs or the A-port outputs or place both

output ports into the high-impedance mode. The

device transmits data from the A bus to the B bus

when the B-port outputs are activated, and from the B

bus to the A bus when the A-port outputs are

activated. The input circuitry on both A and B ports is

always active and must have a logic HIGH or LOW

The SN74LVC8T245-EP is designed so that the

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN74LVC8T245-EP

TSSOP (24)

4.40 mm × 7.80 mm

SOIC (24)

7.50 mm × 15.40 mm

VQFN (24)

3.50 mm × 5.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Logic Diagram (Positive Logic)