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LMC6682AIMX Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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LMC6682AIMX Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 24 page AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for T J = 25˚C, V + = 3V, V− = 0V, V CM = VO = V +/2, V PD = 0.6V and RL > 1 M Ω. Boldface limits apply at the temperature extremes (Note 16). Symbol Parameter Conditions Typ (Note 5) LMC6681AI LMC6681BI Units LMC6682AI LMC6682BI LMC6684AI LMC6684BI Limit Limit (Note 6) (Note 6) t ON Time Delay for (Note 15) 50 200 200 µs Device to Power ON t OFF Time Delay for (Note 15) 0.5 2 2 µs Device to Power OFF SR Slew Rate (Note 8) 1.2 0.7 0.7 V/µs min 0.55 0.55 V + = 10V, (Note 10) 1.2 0.7 0.7 0.55 0.55 GBW Gain-Bandwidth Product 1.2 MHz φ m Phase Margin 50 Deg G m Gain Margin 12 dB Amp-to-Amp Isolation V + = 10V (Note 9) 130 dB e n Input-Referred f = 1 kHz 32 Voltage Noise V CM = 0.5V i n Input-Referred f = 1 kHz 0.5 Current Noise T.H.D. Total Harmonic Distortion f = 1 kHz, A V = +1 0.01 % R L = 10 kΩ,VO = 2VPP Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is in- tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the electrical characteristics. Note 2: Human body model, 1.5 k Ω in series with 100 pF. Note 3: Applies to both single-supply and split-supply operation. Continous short circuit operation at elevated ambient temperature can result in exceeding the maxi- mum allowed junction temperature of 150˚C. Output current in excess of ±30 mA over long term may adversely affect reliability. Note 4: The maximum power dissipation is a function of TJ (max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) −TA)/θJA. All numbers apply for packages soldered directly into a PC board. Note 5: Typical Values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: V+ = 3V, VCM = 0.5V. For sourcing and sinking, 0.5V ≤ VO ≤ 2.5V. Note 8: V+ = 3V. Connected as Voltage Follower with 2V step input, and the output is measured from 15%–85%. Number specified is the slower of the positive or negative slew rates. Note 9: Input referred, V+ = 10V, and RL = 100 kΩ connected to 5V. Each amp excited in turn with 1 kHz to produce VO = 2VPP. Note 10: V+ = 10V. Connected as voltage follower with 8V step Input, and output is measured from 15%–85%. Number specified is the slower of the positive or nega- tive slew rates. Note 11: Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings. Note 12: Guaranteed limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value. Note 13: CMRR+ and CMRR− are tested, and the number indicated is the lower of the two values. For CMRR+,V+/2 < VCM < V + for 1.8V, 2.2V, 3V, 5V, and 10V. For CMRR−,0 < VCM < V +/2 for 3V, 5V and 10V. For 1.8V and 2.2V, 0.25 < V CM < V + − 0.3. Note 14: V+ = 10V, VCM = 0.5V. For Sourcing tests, 1V ≤ VO ≤ 5V. For Sinking tests, 5V ≤ VO ≤ 9V. Note 15: The propogation delays are measured using an input waveform of f = 5 Hz, and magnitude of 2.4V. Refer to Section 6.3 and Figures 14, 15 for a detailed explanation. Note 16: The VPD (threshold low and threshold high) limits are guaranteed at room temperature and at temperature extremes. Room temperature limits are produc- tion tested. Limits at temperature extremes are guaranteed via correlation using temperature regression analysis methods. Refer to Section 6.2 for an overview of the threshold voltages. www.national.com 9 |
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