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73M2910L Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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3 / 35 page 73M2910L Microcontroller 3 REGISTER DESCRIPTION INTERRUPTS The core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt, and an HDLC interrupt. An external interrupt and an HDLC interrupt are unique to the 73M2910L. They do not exist in a normal 8032 product. Previously unused bits in the IE and IP registers are now serving functions for these additional interrupt sources. The interrupt vector addresses are as follows: SOURCE VECTOR ADDRESS INT) (IE0) 003H TF0 00BH INT! (IE1) 013H TF1 01BH RI + TI 023H TF2 + EXF2 02BH INT@ - ADDED INTERRUPT 033H HDLC - ADDED INTERRUPT 03BH The external interrupt sources, INT(2:0), come from dedicated input pins. The apparent polarity of these pins is individually controlled by bits in a special interrupt direction register, IDIR (address A9). The interrupt pins INT! and INT) can be either edge or level generated interrupts as indicated by bits 1 and 3 in the TCON Register (address 88). Pin INT@ is always an edge generated interrupt. A flag is set when a falling transition (rising if IDIR bit 2 is set) on this pin is detected. This flag is automatically cleared when the interrupt is processed. INTERRUPT ENABLE REGISTER (IE) SFR ADDRESS 0A8h Bit Addressable Reset State 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EA EX2 ET2 ES ET1 EX1 ET0 EX0 NOTE: Bit 6 differs from the 8032. This is a reserved bit in the 8032 and is used as a mask bit for external interrupt 2 in the core implementation. When bit 6 is set to a 0, external interrupt 2 is disabled. The mask bit for the HDLC interrupt source is bit 0 of the HDLC Control Register. INTERRUPT PRIORITY REGISTER (IP) SFR ADDRESS 0B8h Bit Addressable Reset State 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PHDLC PX2 PT2 PS PT1 PX1 PT0 PX0 NOTE: Bit 6 and bit 7 differ from the 8032. These are reserved bits in the 8032 and are used to determine the priority of external interrupt 2 and the HDLC in the core implementation. When bit 6 is set to a 1, the interrupt is set to the higher priority level. |
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