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SQ1912AEEH Datasheet(PDF) 10 Page - Vishay Siliconix |
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SQ1912AEEH Datasheet(HTML) 10 Page - Vishay Siliconix |
10 / 12 page Dual-Channel LITTLE FOOT® 6-Pin SC-70 MOSFET Copper Leadframe Version Recommended Pad Pattern and Thermal Performance 175 °C Rated Part Application Note AN917 www.vishay.com Vishay Siliconix Revision: 15-Apr-13 2 Document Number: 75130 For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Fig. 3 THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the dual SC-70 6-pin package is measured as junction-to-foot thermal resistance, in which the “foot” is the drain lead of the device as it connects with the body. The junction-to-foot thermal resistance for this device is typically 80 °C/W, with a maximum thermal resistance of approximately 100 °C/W. This data compares favorably with another compact, dual-channel package - the dual TSOP-6 - which features a typical thermal resistance of 75 °C/W and a maximum of 90 °C/W. Power Dissipation for 175 °C Rated Part The typical R JA for the dual-channel 6-pin SC-70 with a copper leadframe is 224 °C/W steady-state, compared to 413 °C/W for the Alloy 42 version. All figures are based on the 1-inch2 FR4 test board. The following example shows how the thermal resistance impacts power dissipation for the dual 6-pin SC-70 package at varying ambient temperatures. Alloy 42 Leadframe Although they are intended for low-power applications, devices in the 6-pin SC-70 dual-channel configuration will handle power dissipation in excess of 0.5 W. TESTING To further aid the comparison of copper and Alloy 42 leadframes, Figures 4 and 5 illustrate the dual-channel 6-pin SC-70 thermal performance on two different board sizes and pad patterns. The measured steady-state values of R JA for the dual 6-pin SC-70 with varying leadframes are as follows: The results indicate that designers can reduce thermal resistance ( JA) by 34 % simply by using the copper leadframe device as opposed to the Alloy 42 version. In this example, a 174 °C/W reduction was achieved without an increase in board area. If an increase in board size is feasible, a further 120 °C/W reduction can be obtained by utilizing a 1-inch2. PCB area. 6 - 0 7 C S d r a o B f o k c a B 6 - 0 7 C S d r a o B f o t n o r F D1 G2 S2 S1 G1 D2 SC70−6 DUAL vishay.com ALLOY 42 LEADFRAME ROOM AMBIENT 25 °C ELEVATED AMBIENT 60 °C P D T J(max.) - TA R JA P D 175 °C - 25 °C 413 °C/W P D 363 mW T J(max.) - TA 175 °C - 60 °C 413 °C/W P D R JA P D P D 278 mW COOPER LEADFRAME ROOM AMBIENT 25 °C ELEVATED AMBIENT 60 °C LITTLE FOOT 6-PIN SC-70 ALLOY 42 COPPER 1) Minimum recommended pad pattern on the EVB board (see fig. 3). 518 °C/W 344 °C/W 2) Industry standard 1-inch2 PCB with maximum copper both sides. 413 °C/W 224 °C/W P D T J(max.) - TA R JA P D 175 °C - 25 °C 224 °C/W P D 669 mW T J(max.) - TA 175 °C - 60 °C 224 °C/W P D R JA P D P D 513 mW |
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