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ADP3171 Datasheet(PDF) 9 Page - Analog Devices |
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ADP3171 Datasheet(HTML) 9 Page - Analog Devices |
9 / 12 page REV. 0 ADP3171 –9– Power MOSFETs Two external N-channel power MOSFETs must be selected for use with the ADP3171, one for the main switch and one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage (VGS(TH)), the ON resistance (RDS(ON)), and the gate charge (QG). Logic level MOSFETs are highly recommended. Only logic level MOSFETs with VGS ratings higher than the absolute maximum value of VCC should be used. The maximum output current IO(MAX) determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3171 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conduct- ing the average load current. For VIN = 5 V and VOUT = 1.5 V, the maximum duty ratio of the high-side FET is: Df t D kHz s HSF MAX MIN OFF HSF MAX () () – –. % =+ () =× () = 1 1 192 3 5 33 µ (20) The maximum duty ratio of the low-side (synchronous rectifier) MOSFET is: DD LSF MAX HSF MAX () () –% == 167 (21) The maximum rms current of the high-side MOSFET is: ID II I I I AA A A A HSF MAX HSF MAX L VALLEY L VALLEY L PEAK L PEAK HSF MAX () () () () ( ) ( ) () () . .( . . ) . . =× +× + =× +× + = 22 22 3 033 375 3 75 625 6 25 3 29 (22) The maximum rms current of the low-side MOSFET is: ID II I I I AA A A A LSF MAX LSF MAX L VALLEY L VALLEY L PEAK L PEAK LSF MAX () () () ( )() () () () ) . .( . . ) . . =× +× + =× +× + () = 22 22 3 067 375 3 75 625 6 25 3 41 (23) The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the maximum output power is allowed for MOSFET dissipation, the total dissipation will be: PV I PV A mW D FETs OUT OUT MAX D FETs () ( ) () . .. . =× × =× × = 01 01 15 65 975 (24) Allocating half of the total dissipation for the high-side MOSFET and half for the low-side MOSFET, and assuming that the resistive loss of the high-side MOSFET is one-third and the switching loss is two-thirds of its total, the required maximum MOSFET resistances will be: R P I mW A m DS ON HSF D FETs HSF MAX () () () . = × = × = 3 975 32 9 38 22 Ω (25) R P I mW A m DS ON LSF D FETs LSF MAX () () () . = × = × = 2 975 24 1 29 22 Ω (26) Note that there is a trade-off between converter efficiency and cost. Larger MOSFETs reduce the conduction losses and allow higher efficiency, but increase the system cost. A Fairchild FDB6982 dual MOSFET (high-side RDS(ON) = 28 m Ω nominal, 35 mΩ worst-case; and low-side RDS(ON) = 16 m Ω nominal, 22 mΩ worst-case) is a good choice in this application. With this choice, the high-side MOSFET dissipation is: PR I VI Q f I VQ f Pm A AnC kHz A VnC kHz mW HSF DS ON HSF HSF MAX IN L PEAK G MIN G IN RR MIN HSF =× + ×× × × +× × =× + +× × × +× × = () ( ) () . . 2 2 2 35 2 9 56 25 12 192 21 519 192 349 Ω (27) where the second term represents the turn-off loss of the MOSFET and the third term represents the turn-on loss due to the stored charge in the body diode of the low-side MOSFET. In the sec- ond term, QG is the gate charge to be removed from the gate for turn-off and IG is the gate turn-off current. From the data sheet, the value of QG for the FDS6982 is 12 nC and the peak gate drive current provided by the ADP3171 is about 1 A. In the third term, QRR is the charge stored in the body diode of the low-side MOSFET at the valley of the inductor current. The data sheet of the FDS6982 shows a value of 19 nC for this parameter. The low-side MOSFET dissipation is: PR I Pm A mW LSF DS ON LSF LSF MAX LSF =× =×= () ( ) . 2 2 22 4 1 370 Ω (28) Note that there are no switching losses in the low-side MOSFET. CIN Selection and Input Current di/dt Reduction In continuous inductor-current mode, the source current of the high-side MOSFET is a square wave with a duty ratio of VOUT/VlN and an amplitude of one-half of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by: II D D IA A C RMS O HSF HSF C RMS () () – .– . . =× =× = 2 2 50 33 0 332 4 (29) For a ZA-type capacitor with 1000 µF capacitance and 6.3 V voltage rating, the ESR is 24 m Ω and the maximum allowable ripple current at 100 kHz is 2 A. At 105 °C, at least two such capacitors should be connected in parallel to handle the calcu- lated ripple current. At 50 °C ambient, however, a higher ripple current can be tolerated, so one capacitor is adequate. The ripple voltage across the input capacitor is: VI ESR n D nC f VI m mF kHz mV CRIPPLE O C C HSF MAX CIN MIN CRIPPLE O () () () . =× + ×× =× + ×× = 24 1 033 11 192 26 Ω (30) Linear Regulators The linear regulators provide a low-cost, convenient, and versatile solution for generating moderate current supply rails. The maxi- mum output load current is determined by the size and thermal impedance of the external N-channel power MOSFET that is placed in series with the supply and controlled by the ADP3171. The output voltage is sensed at the LRFB × pin and compared to an internal reference voltage in a negative feedback loop that keeps the output voltage in regulation. If the load is reduced or |
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