REV. 0

–10–

ADP3171

increased, the MOSFET drive will also be reduced or increased

by the ADP3171 to provide a well regulated output voltage.

Output voltages higher than the fixed internal reference voltage

can be programmed by adding an external resistor divider. The

correct resistor values for setting the output voltage of the linear

regulators in the ADP3171 can be determined using:

VV

RR

R

OUT LR

LRFB X

UL

L

()

(

)

=×

+

(31)

R

kV

V

V

R

kV

V

V

k

U

OUT(LR)

LRFB

LRFB

U

=

×−

()

=

×−

()

=

10

10

3 3

18

18

833

2

2

Ω

Ω

Ω

..

.

.

(32)

The closest 1% resistor value is 8.25 k

Ω.

Efficiency of the Linear Regulators

The efficiency and corresponding power dissipation of each of the

linear regulators are not determined by the ADP3171. Rather,

these are a function of input and output voltage and load current.

Efficiency is approximated by the formula:

η=

×

100%

V

V

OUT

IN

(33)

The corresponding power dissipation in the MOSFET, together

with any resistance added in series from input to output, is

given by:

PV

V

I

LDO

IN

OUT

OUT

=

–

(34)

Minimum power dissipation and maximum efficiency are

accomplished by choosing the lowest available input voltage that

exceeds the desired output voltage. However, if the chosen input

source is itself generated by a linear regulator, its power dissipa-

tion will be increased in proportion to the additional current it

must now provide.

LAYOUT AND COMPONENT PLACEMENT GUIDELINES

The following guidelines are recommended for optimal performance

of a switching regulator in a PC system:

General Recommendations

1.

For best results, a four-layer PCB is recommended. This

should allow the needed versatility for control circuitry

interconnections with optimal placement, a signal ground

plane, power planes for both power ground and the input

power (e.g., 5 V), and wide interconnection traces in the

rest of the power delivery current paths.

2.

Whenever high currents must be routed between PCB

layers, vias should be used liberally to create several paral-

lel current paths so that the resistance and inductance

introduced by these current paths is minimized and the via

current rating is not exceeded.

3.

If critical signal lines (including the voltage and current

sense lines of the ADP3171) must cross through power

circuitry, it is best if a ground plane can be interposed

between those signal lines and the traces of the power

circuitry. This serves as a shield to minimize noise injection

into the signals at the expense of making signal ground a

bit noisier.

4.

The GND pin of the ADP3171 should connect first to a

ceramic bypass capacitor (on the VCC pin) and then into

the analog ground plane. The analog ground plane should

be located below the ADP3171 and the surrounding

small signal components such as the timing capacitor

and compensation network. The analog ground plane

should connect to power ground plane at a single point; the

best location being the negative terminal of the last

output capacitor.

5.

The output capacitors should also be connected as closely

as possible to the load (or connector) that receives the power

(e.g., a microprocessor core). If the load is distributed, the

capacitors also should be distributed, and generally in pro-

portion to where the load tends to be more dynamic. It is

also advised to keep the planar interconnection path short

(i.e., have input and output capacitors close together).

6.

Absolutely avoid crossing any signal lines over the switching

power path loop, described below.

Power Circuitry

7.

The switching power path should be routed on the PCB to

encompass the smallest possible area in order to minimize

radiated switching noise energy (i.e., EMI). Failure to take

proper precaution often results in EMI problems for the

entire PC system as well as noise-related operational problems

in the power converter control circuitry. The switching power

path is the loop formed by the current path through the

input capacitors, the two FETs, and the power Schottky

diode, if used, including all interconnecting PCB traces and

planes. The use of short and wide interconnection traces is

especially critical in this path for two reasons: it minimizes

the inductance in the switching loop, which can cause high

energy ringing, and it accommodates the high current

demand with minimal voltage loss.

8.

A power Schottky diode (1 ~ 2 A dc rating) placed from the

lower MOSFET’s source (anode) to drain (cathode) will

help to minimize switching power dissipation in the upper

MOSFET. In the absence of an effective Schottky diode,

this dissipation occurs through the following sequence of

switching events. The lower MOSFET turns off in advance

of the upper MOSFET turning on (necessary to prevent

cross conduction). The circulating current in the power

converter, no longer finding a path for current through the

channel of the lower MOSFET, draws current through the

inherent body-drain diode of the MOSFET. The upper

MOSFET turns on, and the reverse recovery characteristic

of the lower MOSFET’s body-drain diode prevents the drain

voltage from being pulled high quickly. The upper MOSFET

then conducts very large current while it momentarily has

a high voltage forced across it, which translates into added

power dissipation in the upper MOSFET. The Schottky diode

minimizes this problem by carrying a majority of the circu-

lating current when the lower MOSFET is turned off, and

by virtue of its essentially nonexistent reverse recovery time.

9.

Whenever a power dissipating component (e.g., a power

MOSFET) is soldered to a PCB, the liberal use of vias, both

directly on the mounting pad and immediately surrounding

it, is recommended. Two important reasons for this are: