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ADSP-21MOD870 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-21MOD870 Datasheet(HTML) 10 Page - Analog Devices |
10 / 32 page ADSP-21mod870 –10– REV. 0 Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-21mod870 has 32K words on Data Memory RAM on chip, consisting of 16,352 user-accessible locations and 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register. Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). The DMOVLAY bits are defined in Table IV. Table IV. DMOVLAY Bits DMOVLAY Memory A13 A12:0 0, 4, 5 Internal Not Applicable Not Applicable 1 External 13 LSBs of Address Overlay 1 0 Between 0x2000 and 0x3FFF 2 External 13 LSBs of Address Overlay 2 1 Between 0x2000 and 0x3FFF I/O Space (Full Memory Mode) The ADSP-21mod870 supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit-wide data. The lower eleven bits of the external address bus are used; the upper 3 bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAIT0-3, which specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table V. Table V. Wait States Address Range Wait State Register 0x000–0x1FF IOWAIT0 0x200–0x3FF IOWAIT1 0x400–0x5FF IOWAIT2 0x600–0x7FF IOWAIT3 Composite Memory Select (CMS) The ADSP-21mod870 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can com- bine their functionality. Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is as- serted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit. The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except BMS. Boot Memory Select (BMS) Disable The ADSP-21mod870 lets you boot the processor from one external memory space while using a different external memory space for BDMA transfers during normal operation. You can use the CMS to select the first external memory space for BDMA transfers and BMS to select the second external space for booting. The BMS signal can be disabled by setting Bit 3 of the system control register to 1. The system control register is illustrated in Figure 7. 0 0 0 0 0 1 00 00 0 0 0 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4321 0 DM (0x3FFF) SYSTEM CONTROL REGISTER SPORT0 ENABLE 1 = ENABLED, 0 = DISABLED SPORT1 ENABLE 1 = ENABLED, 0 = DISABLED SPORT1 CONFIGURE 1 = SERIAL PORT 0 = FI, FO, IRQ0, IRQ1, SCLK PWAIT PROGRAM MEMORY WAIT STATES BMS ENABLE 0 = ENABLED, 1 = DISABLED Figure 7. System Control Register Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K × 8. The byte memory space on the ADSP-21mod870 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register. Byte Memory DMA (BDMA, Full Memory Mode) The byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one processor cycle per 8-, 16- or 24-bit word transferred. BDMA CONTROL BMPAGE BDMA OVERLAY BITS BTYPE BDIR 0 = LOAD FROM BM 1 = STORE TO BM BCR 0 = RUN DURING BDMA 1 = HALT DURING BDMA 00 0 0 0 0 00 000 0 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 43210 DM (0x3FE3) Figure 8. BDMA Control Register The BDMA circuit supports four different data formats which are selected by the BTYPE register field. The appropriate num- ber of 8-bit accesses are done from the byte memory space to build the word size selected. Table VI shows the data formats supported by the BDMA circuit. |
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