3

521 - 01 - 05

SYSTEM DESCRIPTION

The GS9005A Receiver or GS9015A Reclocker along with the

GS9000B or GS9000S Decoder form a serial to parallel decoding

system for Serial Digital Video signals. Use of the GS9010A

eliminates the need to manually tune the VCO and externally

temperature compensate for all data rates. Figure 1 shows a

simplified block diagram of the Automatic Tuning Sub-System

and Figure 2 shows the relevant waveforms.

The active high CARRIER DETECT output of the Receiver/

Reclocker indicates the presence of serial data. If the CARRIER

DETECT input to the GS9010A (pin 14) is HIGH (see Fig 2. [A])

and a Timing Reference Signal (TRS) is not being detected by

the GS9000B or GS9000S Decoder, an oscillator in the GS9010A

produces a sawtooth ramp signal at the OUT pin

(pin 2)(see Figure 2. [C]). This output is connected to the

voltage ramp into a current ramp. The frequency of the VCO is

that a lower sweep voltage at pin 2 of the GS9010A causes a

higher VCO frequency.

As the frequency sweeps, the PLL will lock to the incoming data

stream and the GS9000B or GS9000S decoder will detect TRS.

The TRS detect function is provided by the HSYNC output of the

GS9000B or GS9000S. In this case, HSYNC is a digital signal

which changes state whenever TRS is detected. This signal is

connected to the HSYNC input (pin 13) of the GS9010A (see

Figure 2 [B]). This signal will be at a rate equal to one half the

horizontal scan rate for composite video and equal to the

horizontal scan rate for component video since both EAV and

SAV produce an HSYNC state change. The presence of

detected TRS will shut off the GS9010A oscillator and disable

the sweep. Even though the oscillator is off, the Automatic Fine

Tuning (AFT) function provided by the buffer amplifier in the

GS9010A remains in the control loop in order to centre the

2.3V).

The VCO within the GS9005A or GS9015A has a dual modulus

divider feature which optimises jitter performance for the lower

data rates. This feature is enabled by a logic HIGH on the ƒ/2

pin. The MODULUS CONTROL output (pin 6) (see Figure 2.

[D]) of the GS9010A controls this ƒ/2 function to set the VCO

frequency to twice the normal rate. Under normal operation the

VCO within the GS9005A or GS9015A, operates at twice the

output clock frequency, which means that for 360 Mb/s data the

VCO is operating at 720 MHz (2 x 360 MHz). For 177 Mb/s (PAL

- 4fsc), with the ƒ/2 function enabled, the VCO operates at 708

MHz (2 x 2 x 177 MHz). In the case of component and

composite NTSC, the VCO operates at 540 MHz (2 x 270 MHz)

and 572 MHz (2 x 2 x 143 MHz) respectively. This means that

the VCO is tuned to the same frequency range for 4:2:2 and the

respective 4ƒsc signals.

The MODULUS CONTROL itself is derived by dividing the

GS9010A oscillator by four. It is possible that the PLL could lock

with the MODULUS CONTROL in the wrong state (ƒ/2 OFF) for

component data rates.

In order to avoid this, another circuit ensures that the MODULUS

CONTROL is set HIGH (ƒ/2 ENABLED) for composite data

rates and LOW (ƒ/2 OFF) for component data rates. This is

accomplished through a Frequency Detector (Frequency to

Voltage Convertor, FVC) which measures the frequency of

HSYNC and compares it to a reference. If the frequency of

HSYNC corresponds to composite video, the comparator

output is high and the

÷4 (MODULUS CONTROL) is set HIGH.

Conversely, when the frequency of HSYNC corresponds to

component video, the MODULUS CONTROL is set LOW.

If the FVC measurement results in any change to the MODULUS

CONTROL, the PLL will immediately lose lock, the TRS will not

be detected and the oscillator will begin to sweep the VCO

frequency. Now the PLL will reacquire lock with the MODULUS

CONTROL in the correct state before the

÷4 output changes

state.

In a noisy environment or at power-on, erratic TRS will cause

the GS9000B or GS9000S to output an artificially low HSYNC

frequency. This condition often subsides after input data

stabilizes or in the case of power-up, once the supplies have

settled. The GS9010A employs a technique to provide noise

immunity within the COMPOSITE/COMPONENT DETECTOR

(CCD) to protect against erroneous modulus settings. This

technique is explained in the following paragraph.

A delay is required for the FVC calculation within the CCD

before the

÷4 is set/reset. In the GS9010A, the trigger

threshold for this delay is controlled by the ƒ/2 and FVCAP

output voltage. Because this threshold is modulated, the

incoming HSYNC frequency must be compatible with the

current ƒ/2 state before the delay is triggered. This threshold

control prevents artificially low HSYNC frequencies from

triggering the set/reset of the

÷4 thus preventing the wrong

MODULUS CONTROL.

If the serial digital signal is interrupted, CARRIER DETECT

(pin 14) goes LOW and turns the internal oscillator off. The

buffer from the LOOP FILTER input (pin 5) to the 20 k

Ω

integrator resistor is disabled and its output becomes high

impedance, neither sinking nor sourcing current. In this state,

the output voltage from the GS9010A will remain constant for

a time period of typically 2 seconds. The VCO in the Receiver/

Reclocker will remain tuned to the correct frequency so that

the PLL will relock quickly without frequency sweeping when

the serial data returns. For longer periods of data interruption,

the external integration capacitor between the OUT and IN

pins will slowly discharge and the VCO will drift lower in

frequency. The serial clock output frequency of the PLL will

settle to approximately 170 MHz when ƒ/2 is high and 85 MHz

when ƒ/2 is low. A limit has been set on the maximum OUT

voltage to prevent Receiver/Reclocker VCOshutdown allowing

faster relock time once data is reapplied.