5

521 - 01 - 05

(A) CARRIER

DETECT

(PIN 14)

(C) OUT

(PIN 2)

2 SECONDS

2 MINs

(D) ƒ/2

(PIN 6)

(B) HSYNC

(PIN 13)

TRS

TRS

LOOP

LOCKED

LOOP

LOCKED

COMPONENT VIDEO

COMPOSITE VIDEO

(NOT TO SCALE)

Fig. 2

System Waveform Diagrams

APPLICATIONS

Figure 3 shows a typical application circuit using the GS9010A

in an autotuning SDI receiver.

Correct operation of an autotuning receiver is determined by

using a suitable EDH measurement tool or Digital to Analog

Monitor to verify error free performance.

The correct operation of a locked autotuning receiver can be

verified by referring to Figure 2. The HSYNC output from the

GS9000B or GS9000S decoder will toggle on each occurrence

of the Timing Reference Signal (TRS). The state of the HSYNC

output is not significant, just the rate at which it toggles.

Application Note - PCB Layout

Special attention must be paid to component layout when

designing high performance serial digital receivers.

For background information on high speed circuit and layout

design concepts, refer to Document No. 521-32-00, “Optimizing

Circuit and Layout Design of the GS90005A/15A”. A recom-

mended PCB layout can be found in the Gennum Application

Note “EB9010B Deserializer Evaluation Board”

The use of a star grounding technique is required for the loop

filter components of the GS9005A/15A.

Controlled impedance PCB traces should be used for the

differential clock and data

interconnection between the

GS9005A and the GS9000B or GS9000S. These differential

traces must not pass over any ground plane discontinuities. A

slot antenna is formed when a microstrip trace runs across a

break in the ground plane.

The series resistors at the parallel data output of the

GS9000B/S are used to slow down the fast rise/fall time of the

GS9000B/S outputs. These resistors should be placed as

close as possible to the GS9000B or GS9000S output pins to

minimize radiation from these pins.