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AD7605-4BSTZ Datasheet(PDF) 6 Page - Analog Devices |
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AD7605-4BSTZ Datasheet(HTML) 6 Page - Analog Devices |
6 / 28 page Data Sheet AD7605-4 Rev. 0 | Page 5 of 27 TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. Note that throughout this data sheet, multifunction pins, such as RD/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, RD, when only that function is relevant. Table 3. VINL = 0.1 × VDRIVE and VINH = 0.9 × VDRIVE Logic Input Levels VINL = 0.3 × VDRIVE and VINH = 0.7 × VDRIVE Logic Input Levels Parameter Min Typ Max Min Typ Max Unit Description PARALLEL/SERIAL/BYTE MODE See Figure 2 and Figure 3 tCYCLE 3.33 3.33 μs 1/throughput rate, parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines tCONV 2 2.08 2 2.08 μs Conversion time tWAKE-UP STANDBY 100 100 μs STBY rising edge to CONVST x rising edge; power- up time from standby mode; not shown in Figure 2 or Figure 3 tWAKE-UP SHUTDOWN Not shown in Figure 2 or Figure 3 Internal Reference 30 30 ms STBY rising edge to CONVST x rising edge; power- up time from shutdown mode External Reference 13 13 ms STBY rising edge to CONVST x rising edge; power- up time from shutdown mode tRESET 50 50 ns RESET high pulse width t1 40 45 ns CONVST x high to BUSY high t2 25 25 ns Minimum CONVST x low pulse t3 25 25 ns Minimum CONVST x high pulse t4 0 0 ns BUSY falling edge to CS falling edge setup time t5 0.5 0.5 ms Maximum delay allowed between CONVST A and CONVST B rising edges t6 25 25 ns Maximum time between last CS rising edge and BUSY falling edge t7 25 25 ns Minimum delay between RESET low to CONVST x high PARALLEL/BYTE READ OPERATION See Figure 4, Figure 5, and Figure 7 t8 0 0 ns CS to RD setup time t9 0 0 ns CS to RD hold time t10 RD low pulse width 16 19 ns VDRIVE above 4.75 V 21 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 32 37 ns VDRIVE above 2.3 V t11 15 15 ns RD high pulse width t12 22 22 ns CS high pulse width; CS and RD linked t13 Delay from CS until DB15 to DB0 three-state disabled 16 19 ns VDRIVE above 4.75 V 20 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 37 ns VDRIVE above 2.3 V t14 Data access time after RD falling edge 16 19 ns VDRIVE above 4.75 V 21 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 32 37 ns VDRIVE above 2.3 V |
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