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ACPL-W481 Datasheet(PDF) 7 Page - AVAGO TECHNOLOGIES LIMITED

Part # ACPL-W481
Description  Inverted Logic, High CMR Optocoupler for Intelligent Power Modules and IGBT/MOSFET Gate Drive
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Manufacturer  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Direct Link  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

ACPL-W481 Datasheet(HTML) 7 Page - AVAGO TECHNOLOGIES LIMITED

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Table 7. Package Characteristics
Parameter
Symbol Min.
Typ.
Max. Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage*
VISO
3750
(ACPL-P481)
5000
(ACPL-W481)
Vrms
RH < 50%, t = 1 min.
TA = 25°C
5, 8
Input-Output Resistance
RI-O
1012
VI-O = 500 Vdc
5
Input-Output Capacitance
CI-O
0.6
f = 1 MHz, VI-O = 0 Vdc
5
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable).
Notes:
1. Derate total package power dissipation, PT, linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.
2. Detector requires a VCC of 4.5V or higher for stable operation as output might be unstable if VCC is lower than 4.5V. Be sure to check the power
ON/OFF operation other than the supply current.
3. Duration of output short circuit time should not exceed 10 ms.
4. Input capacitance is measured between pin 1 and pin 3.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the trailing edge of the
output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the leading
edge of the output pulse.
7. CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, VO > 2.0 V. CML
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, VO < 0.8 V.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS (6000 VRMS for ACPL-W481) for
one second (leakage detection current limit, II-O <= 5 µA). This test is performed before the 100% production test for partial discharge (Method b)
shown in the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
9. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH | for any given device.
10. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 is recommended.
11. The difference between tPLH and tPHL between any two devices under the same test condition.


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