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SI5110-BC Datasheet(PDF) 9 Page - Silicon Laboratories |
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SI5110-BC Datasheet(HTML) 9 Page - Silicon Laboratories |
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9 / 26 page  S i5110 Preliminary Rev. 0.41 9 Table 5. AC Characteristics (Receiver PLL) (VDD = 1.8 V ±5%, TA = –40°C to 85°C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Tolerance JTOL(PP) f = 600 Hz 15 30 — UIpp f = 6000 kHz 1.5 3.0 — UIpp f = 100 kHz 1.5 3.0 — UIpp f = 1 MHz 0.15 0.3 — UIpp Acquisition Time TAQ —— 20 µs Input Reference Clock Frequency RCFREQ REFRATE = 1 — 155 167 MHz REFRATE = 0 — 78 83 MHz Reference Clock Duty Cycle RCDUTY 40 50 60 % Reference Clock Frequency Tolerance RCTOL –100 — 100 ppm Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) LOL TBD 600 1000 ppm Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) LOCK TBD 300 TBD ppm Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998. Table 6. AC Characteristics (Transmitter Clock Multiplier) (VDD = 1.8 V ±5%, TA = –40°C to 85°C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Generation JGEN(rms) PRBS 23 0.005 TBD UIRMS Jitter Transfer Bandwidth JBW BWSEL = 0 — — 6 kHz BWSEL = 1 — — 25 kHz Jitter Transfer Peaking — 0.05 0.1 dB Acquisition Time TAQ Valid REFCLK — — 20 µs Input Reference Clock Frequency RCFREQ REFRATE = 1 — 155 167 MHz REFRATE = 0 — 78 84 MHz Input Reference Clock Duty Cycle RCDUTY 40 — 60 % Input Reference Clock Frequency Tolerance RCTOL –100 — 100 ppm Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998. |
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