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PCA9543PW Datasheet(PDF) 4 Page - NXP Semiconductors |
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PCA9543PW Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 15 page Philips Semiconductors Product data sheet PCA9543 2-channel I2C switch with interrupt logic and reset 2004 Oct 01 4 DEVICE ADDRESS Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9543 is shown in Figure 3. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. A1 A0 00 SW00893 1 1 1 R/W FIXED HARDWARE SELECTABLE Figure 3. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation. CONTROL REGISTER Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9543, which will be stored in the control register. If multiple bytes are received by the PCA9543, it will save the last byte received. This register can be written and read via the I2C-bus. SW01025 CHANNEL SELECTION BITS INTERRUPT BITS (READ ONLY) (READ/WRITE) 6 7 CHANNEL 0 CHANNEL 1 INT0 INT1 INT1 INT0 X X B1 B0 6 5 4 2 1 0 7 3 Figure 4. Control Register CONTROL REGISTER DEFINITION One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9543 has been addressed. The 2 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a stop condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Table 1. Control Register; Write — Channel Selection/ Read — Channel Status D7 D6 INT1 INT0 D3 D2 B1 B0 COMMAND X X X X X X X 0 Channel 0 disabled X X X X X X X 1 Channel 0 enabled X X X X X X 0 X Channel 1 disabled X X X X X X 1 X Channel 1 enabled 0 0 0 0 0 0 0 0 No channel selected; power-up/ reset default state NOTE: Channel 0 and 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance. INTERRUPT HANDLING The PCA9543 provides 2 interrupt inputs, one for each channel, and one open drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9543 and the interrupt output will be driven LOW. The channel need not be active for detection of the interrupt. A bit is also set in the Control Register. Bits 4 – 5 of the Control Register correspond to the INT0 and INT1 inputs of the PCA9543, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PCA9543 and read the contents of the Control Register to determine which channel contains the device generating the interrupt. The master can then reconfigure the PCA9543 to select this channel, and locate the device generating the interrupt and clear it. It should be noted that more than one device can be providing an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general purpose inputs if the interrupt feature is not required. If unused, interrupt input(s) must be connected to VDD through a pull-up resistor. Table 2. Control Register Read — Interrupt 7 6 INT1 INT0 3 2 B1 B0 COMMAND X X X 0 X X X X No interrupt on channel 0 X X X 1 X X X X Interrupt on channel 0 X X 0 X X X X X No interrupt on channel 1 X X 1 X X X X X Interrupt on channel 1 NOTE: The two interrupts can be active at the same time. RESET INPUT The RESET input is an active-LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tWL, the PCA9543 will reset its registers and I2C state machine and will deselect all channels. The RESET input must be connected to VDD through a pull-up resistor. POWER-ON RESET When power is applied to VDD, an internal Power-On Reset holds the PCA9543 in a reset state until VDD has reached VPOR. At this point, the reset condition is released and the PCA9543 registers and I2C state machine are initialized to their default states, all zeroes causing all the channels to be deselected. |
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