TMS4C2972

245760 BY 12-BIT

FIELD MEMORY

SMGS671 – OCTOBER 1997

11

POST OFFICE BOX 1443

output enable (OE)

OE is used to enable or disable output pins Q0 to Q11. A logic high on the OE input enables the output to

Q0–Q11, and a logic low disables the output. The internal read address pointer is incremented by cycling SRCK

regardless of OE logic level. The outputs will be clocked into the high-impedance (floating) state if OE is low

the rising edge of SRCK.

Table 2. Read-Cycle State Table

SRCK RISING EDGE

RE

OE

Read-address pointer

Q0 – Q11

High

High

Address pointer increment

Output data

High

Low

Address pointer increment

Hi-Z

Low

High

Address pointer stop

Output data

Low

Low

Address pointer stop

Hi-Z

power up and initialization

When the device is powered up, it is not assured to function properly until at least 100

1.

A minimum of 96 dummy read operations (SRCK cycles)

2.

An RSTR operation

3.

A minimum of 96 dummy write operations (SWCK cycles)

4.

An RSTW operation

Dummy-read cycles/RSTR (operations 1 and 2) must be performed in sequence. Dummy-write cycles/RSTW

(3 and 4) also must be performed in sequence; however, the dummy-read cycles/RSTR and dummy-write

cycles/RSTW (that is, 1 and 2, 3 and 4) can occur simultaneously.

old-/new-data access

There must be a minimum delay of 160 SWCK cycles between writing into memory and reading out from

memory. If reading of the first field starts, with an RSTR operation, before the start of writing the second field

(that is, before the next RSTW operation), then the data just written in will be read out.

The start of reading out the first field of data may be delayed past the beginning of writing in the second field

of data for as many as 39 SWCK cycles. If the RSTR operation for the first field read-out occurs less than

40 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device

assures that the first field (= old data) will still be read out.

In order to read out new data (that is, the second field written in), the delay between RSTW operation and RSTR

operation must be at least 160 SWCK cycles. If the delay between RSTW and RSTR operations is more than

40 but less than 160 cycles, then the data read out will be undetermined, it may be old data or new data or a

combination of old and new data. Such a timing should be avoided.

The above is still valid if write and/or read random-block access mode is used; the 160 SWCK cycles latency

must be fulfilled by the user between any RSTW and RSTR related to the same block address.