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FT230XQ-xxxx Datasheet(PDF) 11 Page - Future Technology Devices International Ltd. |
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FT230XQ-xxxx Datasheet(HTML) 11 Page - Future Technology Devices International Ltd. |
11 / 44 page Copyright © Future Technology Devices International Limited 11 FT230X USB TO BASIC UART IC Version 1.4 Document No.: FT_000566 Clearance No.: FTDI# 260 3.3 CBUS Signal Options The following options can be configured on the CBUS I/O pins. CBUS signal options are common to both package versions of the FT230X. These options can be configured in the internal MTP memory using the software utility FT_PROG or MPROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com). The default configuration is described in Section 8. CBUS Signal Option Available On CBUS Pin Description TRI-STATE CBUS0, CBUS1, CBUS2, CBUS3 IO Pad is tri-stated DRIVE 1 CBUS0, CBUS1, CBUS2, CBUS3 Output a constant 1 DRIVE 0 CBUS0, CBUS1, CBUS2, CBUS3 Output a constant 0 TXDEN CBUS0, CBUS1, CBUS2, CBUS3 Enable transmit data for RS485 PWREN# CBUS0, CBUS1, CBUS2, CBUS3 Output is low after the device has been configured by USB, then high during USB suspend mode. This output can be used to control power to external logic P-Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# in this way. TXLED# CBUS0, CBUS1, CBUS2, CBUS3 Transmit data LED drive – pulses low when transmitting data via USB. See Section 7.5 for more details. RXLED# CBUS0, CBUS1, CBUS2, CBUS3 Receive data LED drive – pulses low when receiving data via USB. See Section 7.5 for more details. TX&RXLED# CBUS0, CBUS1, CBUS2, CBUS3 LED drive – pulses low when transmitting or receiving data via USB. See Section 7.5 for more details. SLEEP# CBUS0, CBUS1, CBUS2, CBUS3 Goes low during USB suspend mode. Typically used to power down an external TTL to RS232 level converter IC in USB to RS232 converter designs. CLK24MHz CBUS0, CBUS1, CBUS2, CBUS3 24 MHz Clock output.* CLK12MHz CBUS0, CBUS1, CBUS2, CBUS3 12 MHz Clock output.* CLK6MHz CBUS0, CBUS1, CBUS2, CBUS3 6 MHz Clock output.* GPIO CBUS0, CBUS1, CBUS2, CBUS3 CBUS bit bang mode option. Allows up to 4 of the CBUS pins to be used as general purpose I/O. Configured individually for CBUS0, CBUS1, CBUS2 and CBUS3 in the internal MTP memory. A separate application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes in more detail how to use CBUS bit bang mode. BCD Charger CBUS0, CBUS1, CBUS2, CBUS3 Battery charge Detect, indicates when the device is connected to a dedicated battery charger host. Active high output. BCD Charger# CBUS0, CBUS1, CBUS2, CBUS3 Inverse of BCD Charger BitBang_WR# CBUS0, CBUS1, CBUS2, CBUS3 Synchronous and asynchronous bit bang mode WR# strobe output. BitBang_RD# CBUS0, CBUS1, CBUS2, CBUS3 Synchronous and asynchronous bit bang mode RD# strobe output. |
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