UPD72874GC-YEB datasheet(10/40 Pages) NEC

Part #	UPD72874GC-YEB

Description	IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER

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Manufacturer	NEC [NEC]

Direct Link	http://www.nec.com/

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Preliminary Data Sheet S15306EJ2V0DS

10

µµµµPD72874

1.2 PHY Signals: (20 pins)

Name

I/O

Pin No.

IOL

Volts(V)

Function

Block *

TpA0p

I/O

101

-

Port-1 Twisted Pair A Positive Input/Output Note 1

PHY Analog

TpA0n

I/O

100

-

Port-1 Twisted Pair A Negative Input/Output Note 1

PHY Analog

TpB0p

I/O

99

-

Port-1 Twisted Pair B Positive Input/Output Note 1

PHY Analog

TpB0n

I/O

98

-

Port-1 Twisted Pair B Negative Input/Output Note 1

PHY Analog

TpA1p

I/O

105

-

Port-2 Twisted Pair A Positive Input/Output Note 1

PHY Analog

TpA1n

I/O

104

-

Port-2 Twisted Pair A Negative Input/Output Note 1

PHY Analog

TpB1p

I/O

103

-

Port-2 Twisted Pair B Positive Input/Output Note 1

PHY Analog

TpB1n

I/O

102

-

Port-2 Twisted Pair B Negative Input/Output Note 1

PHY Analog

TpA2p

I/O

110

-

Port-3 Twisted Pair A Positive Input/Output Note 1

PHY Analog

TpA2n

I/O

109

-

Port-3 Twisted Pair A Negative Input/Output Note 1

PHY Analog

TpB2p

I/O

108

-

Port-3 Twisted Pair B Positive Input/Output Note 1

PHY Analog

TpB2n

I/O

107

-

Port-3 Twisted Pair B Negative Input/Output Note 1

PHY Analog

CPS

I

93

-

Cable Power Status Input Note2

PHY Digital

TpBias0

O

96

-

Port-1 Twisted Pair Bias Voltage Output Note 1

PHY Analog

TpBias1

O

97

-

Port-2 Twisted Pair Bias Voltage Output Note 1

PHY Analog

TpBias2

O

111

-

Port-3 Twisted Pair Bias Voltage Output Note 1

PHY Analog

RI0

-

91

-

Resistor0 for Reference Current Setting Note 3

PHY Analog

RI1

-

92

-

Resistor1 for Reference Current Setting Note 3

PHY Analog

XI

I

87

-

X’tal XI

PHY Analog

XO

O

88

-

X’tal XO

PHY Analog

Notes 1. If unused port, please refer to 4.1.4 Unused Ports.

2. Please refer to 4.1.3 CPS.

3. Please refer to 4.5 RI0, RI1.

Remark *: If the PHY Digital pin is pulled up, it should be connected to P_DVDD.

If the PHY Analog pin is pulled up, it should be connected to P_AVDD.

1.3 PHY Control Signals: (4 pins)

Name

I/O

Pin No.

IOL

Volts(V)

Function

Block *

PC0 to PC2

I

70 to 72

-

3.3

Power Class Input Note 1

PHY Digital

P_RESET

I

81

-

PHY Power on Reset Input Note 2

PHY Digital

Notes 1. Please refer to 4.3 PC0 to PC2.

2. Please refer to 4.4 P_RESET.

Remark *: If the PHY Digital pin is pulled up, it should be connected to P_DVDD.

1.4 PCI/Cardbus Select Signal: (1 pin)

Name

I/O

Pin No.

IOL

Volts(V)

Function

Block *

CARD_ON

I

119

-

3.3

PCI/CardBus Select

1:Cardbus mode

0:PCI bus mode

Link

Remark *: If the Link pin is pulled up, it should be connected to L_VDD.

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