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A3980 Datasheet(PDF) 12 Page - Allegro MicroSystems |
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A3980 Datasheet(HTML) 12 Page - Allegro MicroSystems |
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12 / 18 page  Automotive DMOS Microstepping Driver with Translator A3980 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com as shown in table 3. In all other modes, VREF should not be allowed to exceed 4 V, because the peak sense value can reach VREF ⁄ 8, or 100%. Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The one shot off-time, tOFF, is determined for each of the two phases by the combi- nation of an external resistor (RT) and a capacitor (CT). One combination is connected from the timing terminal RC1 to ground, and the other similarly connected to RC2 . tOFF (ns) is approximated by tOFF = RT × CT over a range of values from CT= 470 pF to 1500 pF and from RT = 12 kΩ to 100 kΩ. RC Blanking. In addition to the fixed off-time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching tran- sients related to the capacitance of the load. The blank time, tBLANK (ns), can be approximated by tBLANK = 1400 × CT where CT is the value of the capacitor CT (nF). The blank time should be as short as possible, without caus- ing a false fault detection, to ensure that power dissipation during a fault condition is minimized. The blank time also defines the minimum duration of time that the full-bridge DMOS outputs cause the load current to rise. To ensure correct detection of motor faults, the minimum on-time is extended by an additional fault sampling time, tSCT. The minimum on-time, tMINON is then tMINON = tBLANK + tSCT Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side DMOS gates. A 100 nF ceramic capacitor (CCP), capable of withstanding the battery volt- age VBATT, should be connected between CP1 and CP2. In addition, a 100 nF ceramic capacitor (CCS)is required between VCP and VBB, to act as a reservoir for operating the high-side DMOS devices. The voltage on CCS is limited to the charge pump voltage, which is always less than 10 V. VREG (VREG). This internally-generated voltage is used to operate the sink-side DMOS FETs. The VREG terminal must be decoupled with a 220 nF (10V) capacitor to ground. VREG is internally monitored. In the case of a fault condi- tion, the DMOS outputs of the A3980 are disabled. Enable Input (ENABLE). This input simply turns off all of the DMOS outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs (STEP, DIR, MS1, and MS2), as well as the internal sequencing logic, all remain active, independent of the ENABLE input state. Sleep Mode (SLEEP). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output DMOS FETs, voltage regulator, and charge pump. A logic low on the SLEEP termi- nal puts the A3980 into Sleep mode. A logic high allows nor- mal operation, as well as start-up (at which time the A3980 drives the motor to the Home microstep position). If the A3980 comes out of Sleep mode when VBB is greater than VOVB – VOVBH and less than VOVB, the A3980 will remain in safety mode until VBB is reduced below VOVB - VOVBH. Percent Fast Decay Input (PFD). When a STEP input signal commands an output current level that is lower than that of the previous step, it switches the output current decay to slow, fast, or mixed decay mode, depending on the voltage level at the PFD input, as shown in the following table. Lower PFD Input Voltage Level Decay Mode VPFD >(0.6 × VDD) Slow (0.21 × VDD ) ≤ VPFD≤ (0.6 × VDD) Mixed VPFD < (0.21 × VDD) Fast |
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