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HCF4017B Datasheet(PDF) 6 Page - STMicroelectronics |
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HCF4017B Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 11 page HCF4017B 6/11 TYPICAL APPLICATIONS DIVIDE BY N COUNTER(N < 10) WITH DECODED OUTPUTS When the Nth decoded output is reached (Nth clock pulse) the S-R flip-flop (constructed from two NOR gates of the HCF4001B) generates a reset pulse which clears the HCF4017B to its zero count. At this time, if the Nth decoded output is greater than or equal to 6, the COUT line goes high to clock the next HCF4017B counter section. The "0" decoded output also goes high at this time. Coincidence of the clock low and decoded "0" output high resets the S-R flip-flop to enable the HCF4017B. If the Nth decoded output is less than 6, the COUT line will not go high and, therefore, cannot be used. In this case "0" decoded output may be used to perform the clocking function for the next counter. TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) |
Similar Part No. - HCF4017B |
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Similar Description - HCF4017B |
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