JUNE 2003

DSC-4876/09

1

©2003 Integrated Device Technology, Inc.

Features

x

x

x

x

x

128K x 36, 256K x 18 memory configurations

x

x

x

x

x

Supports high system speed:

Commercial and Industrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

x

x

x

x

x

LBO input selects interleaved or linear burst mode

x

x

x

x

x

Self-timed write cycle with global write control (

GW),bytewrite

enable (

BWE), and byte writes (BWx)

x

x

x

x

x

3.3V core power supply

x

x

x

x

x

Power down controlled by ZZ input

x

x

x

x

x

2.5V I/O

x

x

x

x

x

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

x

x

x

x

x

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

Description

The IDT71V2576/78 are high-speed SRAMs organized as 128K x

36/256K x 18. The IDT71V2576/78 SRAMs contain write, data, address

and control registers. Internal logic allows the SRAM to generate a self-

timedwritebaseduponadecisionwhichcanbeleftuntiltheendofthewrite

cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V2576/78 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(

ADV=LOW),thesubsequentthreecyclesofoutput

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO input pin.

The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array (fBGA).

Pin Description Summary

NOTE:

1.

Address Inputs

Input

Synchronous

CE

Chip Enable

Input

Synchronous

Chip Selects

Input

Synchronous

OE

Output Enable

Input

Asynchronous

GW

Global Write Enable

Input

Synchronous

BWE

Byte Write Enable

Input

Synchronous

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV

Burst Address Advance

Input

Synchronous

ADSC

Address Status (Cache Controller)

Input

Synchronous

ADSP

Address Status (Processor)

Input

Synchronous

LBO

Linear / Interleaved Burst Order

Input

DC

TMS

Test Mode Select

Input

Synchronous

TDI

Test Data Input

Input

Synchronous

TCK

Test Clock

Input

N/A

TDO

Test Data Output

Output

Synchronous

TRST

JTAG Reset (Optional)

Input

Asynchronous

ZZ

Sleep Mode

Input

Asynchronous

Data Input / Output

I/O

Synchronous

Core Power, I/O Power

Supply

N/A

Ground

Supply

N/A

4876 tbl 01

128K X 36, 256K X 18

3.3V Synchronous SRAMs

2.5V I/O, Pipelined Outputs,

Burst Counter, Single Cycle Deselect

IDT71V2576S

IDT71V2578S

IDT71V2576SA

IDT71V2578SA