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IDT7054L25PRFI Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT7054L25PRFI Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 11 page  6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges 8 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to “Timing Waveform of Write Cycle”, Note 8). 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”. 5. 'X' in part number indicates power rating. 7054X20 Com'l Only 7054X25 Com'l, Ind & Military 7054X35 Com'l & Military Symbol Parameter Min.Max.Min. Max.Min.Max. Unit WRITE CYCLE tWC Write Cycle Time 20 ____ 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width (3) 15 ____ 20 ____ 30 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 15 ____ 15 20 ____ ns tHZ Output High-Z Time(1,2) ____ 15 ____ 15 ____ 15 ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns tWZ Write Enable to Output in High-Z(1,2) ____ 12 ____ 15 ____ 15 ns tOW Output Active from End-of-Write(1,2) 0 ____ 0 ____ 0 ____ ns tWDD Write Pulse to Data Delay (4) ____ 35 ____ 45 ____ 55 ns tDDD Write Data Valid to Read Data Delay(4) ____ 30 ____ 35 ____ 45 ns 3241 tbl 10 |
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