6.42

IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

11

NOTES:

2.

3. Multiple bytes may be selected during the same cycle.

NOTES:

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

Operation

GW

BWE

Read

H

H

X

XXX

Read

H

L

HH

HH

Write all Bytes

L

XX

XXX

Write all Bytes

H

LL

LL

L

HL

L

H

H

H

HL

HL

H

H

HL

H

H

L

H

HL

H

H

HL

4876 tbl 12

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

A1

A0

A1

A0

A1

A0

First Address

000

11

0

1

1

Second Address

0

1

1

0

1

1

0

0

Third Address

1

0

1

1

0

0

0

1

11

00

0

1

1

0

4876 tbl 15

S equence 1

S equence 2

S equence 3

S equence 4

A1

A0

A1

A0

A1

A0

A1

A0

Firs t A d dres s

0

0

0

1

1

0

1

1

Se c o nd Ad d re s s

0

1

0

0

1

1

1

0

Third A d dres s

1

0

1

1

0

0

0

1

Fo urth A ddres s

(1)

1

1

1

0

0

1

0

0

4876 tbl 14

Operation

(2)

OE

ZZ

I/O Status

Power

Read

L

L

Data Out

Active

Read

H

L

High-Z

Active

Write

X

L

High-Z – Data In

Active

Deselected

X

L

High-Z

Standby

Sleep Mode

X

H

High-Z

Sleep

4876 tbl 13