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RC0603FR-07140KL Datasheet(PDF) 2 Page - Vishay Siliconix |
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RC0603FR-07140KL Datasheet(HTML) 2 Page - Vishay Siliconix |
2 / 23 page SiC462 www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 2 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PIN CONFIGURATION Fig. 2 - SiC462 Pin Configuration PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION 1VCIN Supply voltage for internal regulators VDD and VDRV. This pin should be tied to VIN, but can also be connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators 2PGOOD Open-drain power good indicator - high impedance indicates power is good. An external pull-up resistor is required 3 EN Enable pin 4 BOOT High-side driver bootstrap voltage 5, 6 PHASE Return path of high-side gate driver 7, 8, 29 VIN Power stage input voltage. Drain of high-side MOSFET 9, 10, 11, 17, 30 PGND Power ground 12, 13, 14 SW Power stage switch node 15 GL Low-side MOSFET gate signal 16 VDRV Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, VDRV is the LDO output. Connect a 4.7 μF decoupling capacitor to PGND 18 ULTRASONIC Float to disable ultrasonic mode, connect to VDD to enable. Depending on the operation mode set by the MODE pin, power save mode or forced continuous mode will be enabled when the ultrasonic mode is disabled 19 SS Set the soft start ramp by connecting a capacitor to AGND. An internal current source will charge the capacitor 20 VSNS Power inductor signal feedback pin for system stability compensation 21 COMP Output of the internal error amplifier. The feedback loop compensation network is connected from this pin to the VFB pin 22 VFB Feedback input for switching regulator used to program the output voltage - connect to an external resistor divider from VOUT to AGND 23, 28 AGND Analog ground 24 fSW Set the on-time by connecting a resistor to AGND 25 ILIMIT Set the current limit by connecting a resistor to AGND 26 VDD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND 27 MODE Set various operation modes by connecting a resistor to AGND. See specification table for details 6 SS 19 ULTRASONIC 1 8 P GND 17 V DRV 16 GL 1 5 SW 1 4 SW 1 3 SW 1 2 1 V CIN 2 P GOOD 3 EN 4 BOOT 5 PHASE 6 PHASE 28 A GND 29 V IN 30 P GND 19 SS 18 ULTRASONIC 17 P GND 16 V DRV 15 GL 14 SW 13 SW 12 SW 1 2 3 4 5 6 28 AGND 30 VIN 29 PGND 1 6 V CIN P GOOD EN BOOT PHASE PHASE |
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