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ADL5910 Datasheet(PDF) 11 Page - Analog Devices |
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ADL5910 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 22 page  Data Sheet ADL5910 Rev. 0 | Page 11 of 22 THEORY OF OPERATION The ADL5910 is a threshold detector with a 45 dB of detection range at 1.9 GHz and a useable range up to 6 GHz. It features no error ripple over its range, low temperature drift, and very low power consumption. R ENVELOPE DETECTOR + – Q S ADL5910 VPOS GND RST Q RFIN VIN– ENBL Q 1 11 DNC 3 1 4 5 7 12 13 Q 16 15 VCAL DECL 4 2 9 10 6 8 Figure 12. Functional Block Diagram The output of the envelope detector drives the noninverting input of a threshold detecting comparator. The inverting input of this comparator is typically driven by a fixed external dc voltage. When the output of the envelope detector exceeds the voltage on the inverting input of the comparator, the comparator goes high. This excursion is then captured and held by an SR flip flop. The state of this flip flop is then held until the level sensitive RST pin is taken high. VIN− = Slope × (VRFIN − Intercept) (1) − × × = − − Intercept P R Slope VIN IN 3 1 10 10 log (2) BASIC CONNECTIONS The ADL5910 requires a single supply of 3.3 V. The supply is connected to the VPOS supply pins. Decouple these pins using two capacitors with values equal or similar to those shown in Figure 13. Place these capacitors as close to Pin 5 as possible. Connect Pin 11 (GND) and the exposed pad to a ground plane with low electrical and thermal impedance. A single-ended input at the RFIN pin drives the ADL5910. Because the input is dc-coupled, an external ac coupling capacitor must be used. A 470 nF capacitor is recommended for applications that require frequency coverage from 6 GHz down to tens of kilohertz. For applications that do not need such low frequency coverage, a larger value of capacitance can be used. In addition to the ac-coupling capacitor, an external 82.5 Ω shunt resistor is required to provide a wideband input match. Figure 11 shows a comparison of the input return loss, with and without the external shunt resistor. The DECL pin provides a bypass capacitor connection for an on-chip regulator. The DECL pin is connected to ground with a 4.02 Ω resistor and a 0.1 µF capacitor. The ENBL pin configures the device enable interface. Connecting the ENBL pin to a logic high signal (2 V to VPOS) enables the device, and connecting the pin to a logic low signal (0 V to 0.6 V) disables the device. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane. VPOS 3.3V THRESHOLD VOLTAGE INPUT RESET INPUT CALIBRATION VOLTAGE OUTPUT 4.0 2Ω 0.1µF 100pF 0.1µF ENABLE/ DISABLE R ENVELOPE DETECTOR + – Q S ADL5910 VPOS GND RST Q RFIN 470nF VIN– DECL 82.5Ω ENBL VCAL Q 1 11 3 1 4 5 7 12 13 Q Q Q 4 16 15 RFIN DNC 2 6 8 10 9 Figure 13. Basic Connections |
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