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TMS320F280049M Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320F280049M Datasheet(HTML) 1 Page - Texas Instruments |
1 / 214 page Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TMS320F280049M SPRS945 – JANUARY 2017 TMS320F28004x Piccolo™ Microcontrollers 1 Device Overview 1 1.1 Features 1 • TMS320C28x 32-Bit CPU – 100 MHz – IEEE 754 Single-Precision Floating-Point Unit (FPU) – Trigonometric Math Unit (TMU) – 3×-Cycle to 4×-Cycle Improvement for Common Trigonometric Functions Versus Software Libraries – 13-Cycle Park Transform – Viterbi/Complex Math Unit (VCU-I) • Programmable Control Law Accelerator (CLA) – 100 MHz – IEEE 754 Single-Precision Floating-Point Instructions – Executes Code Independently of Main CPU • On-Chip Memory – 256KB (128KW) of Flash (ECC-Protected) Across Two Independent Banks – 100KB (50KW) of RAM (ECC-Protected or Parity-Protected) – Dual-Zone Security Supporting Third-Party Development • Clock and System Control – Two Internal Zero-Pin 10-MHz Oscillators – On-Chip Crystal Oscillator and External Clock Input – Windowed Watchdog Timer Module – Missing Clock Detection Circuitry • 1.2-V Core, 3.3-V I/O Design – Internal VREG or Internal Switching Regulator for 1.2-V Generation Allows for Single-Supply Designs • System Peripherals – 6-Channel Direct Memory Access (DMA) Controller – 40 Individually Programmable Multiplexed General-Purpose Input/Output (GPIO) Pins – 21 Digital Inputs on ADC Pins – Enhanced Peripheral Interrupt Expansion (ePIE) Module – Multiple Low-Power Mode (LPM) Support With External Wakeup • Communications Peripherals – One Power Management Bus (PMBus) Interface – One Inter-Integrated Circuit (I2C) Interface (Pin-Bootable) – Two Controller Area Network (CAN) Bus Ports (Pin-Bootable) – Two Serial Peripheral Interface (SPI) Ports (Pin-Bootable) – Two Serial Communication Interfaces (SCIs) (Pin-Bootable) – One Local Interconnect Network (LIN) – One Fast Serial Interface (FSI) With a Transmitter and Receiver • Analog System – Three 3.45-MSPS, 12-Bit Analog-to-Digital Converters (ADCs) – Up to 21 External Channels – Hardware-Integrated Post-Processing of ADC Conversions – Saturating Offset Calibration – Error From Set Point Calculation – High, Low, and Zero Crossing Compare With Interrupt Capability – Trigger-to-Sample Delay Capture – Seven Windowed Comparators (CMPSS) With 12-Bit Reference Digital-to-Analog Converters (DACs) – Digital Glitch Filters – Two 12-Bit Buffered DAC Outputs – Seven Programmable Gain Amplifiers (PGAs) (Gain Settings: 3, 6, 12, 24) • Enhanced Control Peripherals – 16 ePWM Channels With High-Resolution Capability (150-ps Resolution) – Integrated Dead-Band Support With High Resolution – Integrated Hardware Trip Zones (TZs) – Seven Enhanced Capture (eCAP) Modules – Two Enhanced Quadrature Encoder Pulse (eQEP) Modules With Support for CW/CCW Operation Modes – Four Sigma-Delta Filter Module (SDFM) Input Channels (Two Parallel Filters per Channel) – Standard SDFM Data Filtering – Comparator Filter for Fast Action for Overvalue or Undervalue Condition |
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