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ADC12D1620CCMLS Datasheet(PDF) 10 Page - Texas Instruments |
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ADC12D1620CCMLS Datasheet(HTML) 10 Page - Texas Instruments |
10 / 82 page VDR DR GND + - + - VDR DR GND + - + - 10 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Product Folder Links: ADC12D1620QML-SP Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions: Analog Front-End and Clock Pins (continued) PIN TYPE DESCRIPTION EQUIVALENT CIRCUIT NAME NO. VDR A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15 P Power supply for the output drivers NONE VE A8, B9, C8, V8, W9, Y8 P Power supply for the digital encoder NONE VTC G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4 P Power supply for the track-and-hold and clock circuitry NONE HIGH-SPEED DIGITAL OUTPUT PINS DCLKI+, DCLKI– DCLKQ+, DCLKQ– K19/K20 L19/L20 O Data clock output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and, if used, terminate with a 100-Ω differential resistor placed as closely as possible to the differential receiver. Delayed and non-delayed data outputs are supplied synchronously to this signal. The DCLK rates for all of the available modes can be found in Table 8. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. DI11+, DI11– DI10+, DI10– DI9+, DI9– DI8+, DI8– DI7+, DI7– DI6+, DI6– DI5+, DI5– DI4+, DI4– DI3+, DI3– DI2+, DI2– DI1+,DI1 – DI0+, DI0– · DQ11+, DQ11– DQ10+, DQ10– DQ9+, DQ9– DQ8+, DQ8– DQ7+, DQ7– DQ6+, DQ6– DQ5+, DQ5– DQ4+, DQ4– DQ3+, DQ3– DQ2+, DQ2– DQ1+, DQ1– DQ0+, DQ0– J18/J19 H19/H20 H17/H18 G19/G20 G17/G18 F18/F19 E19/E20 D19/D20 D18/E18 C19/C20 B19/B20 B18/C17 · M18/M19 N19/N20 N17/N18 P19/P20 P17/P18 R18/R19 T19/T20 U19/U20 U18/T18 V19/V20 W19/W20 W18/V17 O I- and Q-channel digital data outputs. In non-demux mode, this LVDS data is transmitted at the sampling clock rate. In demux mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data; that is, the other ½ of the data which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. If used, terminate each of these outputs with a 100-Ω differential resistor placed as closely as possible to the differential receiver. |
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