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PC87303 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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PC87303 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 114 page  10 Pin Description (Continued) TABLE 1-1 Pin Descriptions (Alphabetical) (Continued) Symbol Pin IO Function DCD12 114 106 I Data Carrier Detect When low this signal indicates that the MODEM or data set has detected the data carrier The DCD signal is a MODEM status input whose condition the CPU can test by reading bit 7 (DCD) of the MODEM Status Register (MSR) for the appropriate serial channel Bit 7 is the complement of the DCD signal Bit 3 (DDCD) of the MSR indicates whether the DCD input has changed state since the previous reading of the MSR Note Whenever the DDCD bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled DENSEL 77 O Density Select Indicates that a high FDC density data rate (500 kbps or 1 Mbps) or a low density data rate (250 kbps or 300 kbps) is selected DENSEL is active high for high density (525 drives) when IDENT is high and active low for high density (35 drives) when IDENT is low DENSEL is also programmable via the Mode command (see Section 426) DIR 69 O Direction This output determines the direction of the floppy disk drive (FDD) head movement (active e step in inactive e step out) during a seek operation During reads or writes DIR is inactive DR01 73 74 O Drive Select 01 These are the decoded Drive Select outputs that are controlled by the Digital Output Register bits D0D1 The Drive Select outputs are gated with DOR bits 4 – 7 These are active low outputs They are encoded with information to control four FDDs when bit 4 of the Function Enable Register (FER) is set (See MTR01 for more information) DR23 78 O Drive 2 or 3 DR23 is asserted when either Drive 2 or Drive 3 is accessed (except during logical drive exchange see bit 3 of TDR) This pin is configured when bit 1 of ASC is 1 (See DRV2 for further information) DRATE01 83 82 O Data Rate 01 These outputs reflect the currently selected FDC data rate (bits 0 and 1 in the Configuration Control Register (CCR) or the Data Rate Select Register (DSR) whichever was written to last) These pins are totem-pole buffered outputs (6 mA sink 6 mA source) (See MSEN01 for further information) DRID01 90 87 I Drive ID These pins accept input from the floppy disk drive which indicates the type of drive in use These pins should be tied low if they are not used DRID01 is configured when bit 2 of ASC is 1 (See IOCS16 IDEHI and VLD0 for further information) DRV2 78 I Drive2 This input indicates whether a second floppy disk drive has been installed The state of this pin is available from Status Register A in PS2 mode This pin is confgured when bit 1 of ASC is 0 (See DR23 for further information) DSKCHG 60 I Disk Change This input indicates if the drive door has been opened The state of this pin is available from the Digital Input register This pin can also be configured as the Read Gate (RGATE) data separator diagnostic input via the Mode command (see Section 426) DSR12 113 105 I Data Set Ready When low this signal indicates that the data set or MODEM is ready to establish a communications link The DSR signal is a MODEM status input whose condition the CPU can test by reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel Bit 5 is the complement of the DSR signal Bit 1 (DDSR) of the MSR indicates whether the DSR input has changed state since the previous reading of the MSR Note Whenever the DDSR bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled DSTRB 116 O Data Strobe This signal is used in EPP mode as a data strobe It is active low (See AFD and Table 7-5 for further information) DTR12 108 98 O Data Terminal Ready When low this output indicates to the MODEM or data set that the UART is ready to establish a communications link The DTR signal can be set to an active low by programming bit 0 (DTR) of the MODEM Control Register to a high level A Master Reset operation sets this signal to its inactive (high) state Loop mode operation holds this signal to its inactive state (See CFG0 – 4 for further information) ERR 117 I Error A connected printer sets this input low when it has detected an error This pin has a nominal 25 kX pull-up resistor attached to it FDACK 28 I DMA Acknowledge Active low input to acknowledge the FDC DMA request and enable the RD and WR inputs during a DMA transfer When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the Digital Output Register (DOR) When in PS2 mode FDACK is always enabled and bit D3 of the DOR is reserved FDACK should be held high during IO accesses 11 |
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