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SC2200 Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # SC2200
Description  Thin Client On a Chip
Download  433 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SC2200 Datasheet(HTML) 6 Page - National Semiconductor (TI)

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Revision 3.0
Table of Contents (Continued)
4.5.3
RTC Registers . . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 120
4.5.3.1
Usage Hints ... ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 124
4.5.4
RTC General-Purpose RAM Map . ... ... ... .... ... ... ... .... ... ... ... ... 124
4.6
SYSTEMWAKEUP CONTROL (SWC) ... ... ... ... .... ... ... ... .... ... ... ... ... 125
4.6.1
Event Detection . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 125
4.6.1.1
Audio Codec Event ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 125
4.6.1.2
CEIRAddress . ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 125
4.6.2
SWC Registers . . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 126
4.7
ACCESS.BUS INTERFACE . . ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 130
4.7.1
Data Transactions ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 130
4.7.2
Start andStop Conditions ... ... ... ... ... .... ... ... ... .... ... ... ... ... 130
4.7.3
Acknowledge (ACK) Cycle ... ... ... ... ... .... ... ... ... .... ... ... ... ... 131
4.7.4
Acknowledge After Every Byte Rule .. ... ... .... ... ... ... .... ... ... ... ... 132
4.7.5
Addressing Transfer Formats . ... ... ... ... .... ... ... ... .... ... ... ... ... 132
4.7.6
Arbitration on theBus ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 132
4.7.7
Master Mode ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 132
4.7.7.1
MasterStop ... ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 133
4.7.8
Slave Mode . ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 134
4.7.9
Configuration ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 134
4.7.10
ACB Registers . . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 135
4.8
LEGACY FUNCTIONAL BLOCKS .... ... ... ... ... .... ... ... ... .... ... ... ... ... 138
4.8.1
ParallelPort . ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 138
4.8.1.1
ParallelPortRegisterand BitMaps . . ... ... ... .. ... ... ... ... .. ... ... .. 138
4.8.2
UARTFunctionality (SP1 and SP2) .. ... ... .... ... ... ... .... ... ... ... ... 140
4.8.2.1
UART Mode Register Bank Overview ... ... ... .. ... ... ... ... .. ... ... .. 140
4.8.2.2
SP1 and SP2 Register and Bit Maps for UART Functionality . . . . . . . . . . . . . . . 140
4.8.3
IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality . . . . . . . . . . . . 144
4.8.3.1
IR/SP3Mode Register Bank Overview .. ... ... .. ... ... ... ... .. ... ... .. 144
4.8.3.2
IRCP/SP3 Register and Bit Maps ... ... ... ... .. ... ... ... ... .. ... ... .. 144
5.0
Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.1
FEATURE LIST . .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 150
5.2
MODULE ARCHITECTURE . . . . . .... ... ... ... ... .... ... ... ... .... ... ... ... ... 151
5.2.1
Fast-PCIInterface to External PCIBus .. ... .... ... ... ... .... ... ... ... ... 152
5.2.1.1
Processor Mastered Cycles .. .. ... ... ... ... .. ... ... ... ... .. ... ... .. 152
5.2.1.2
External PCI Mastered Cycles .. ... ... ... ... .. ... ... ... ... .. ... ... .. 152
5.2.1.3
CoreLogic Internal or Sub-ISA Mastered Cycles . . ... ... ... ... .. ... ... .. 152
5.2.1.4
External PCI Bus . . ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 152
5.2.1.5
Bus Master Request Priority . . . . ... ... ... ... .. ... ... ... ... .. ... ... .. 152
5.2.2
PSERIAL Interface . . ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 152
5.2.2.1
Video Retrace Interrupt ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 152
5.2.3
IDE Controller ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 153
5.2.3.1
IDE Configuration Registers .. .. ... ... ... ... .. ... ... ... ... .. ... ... .. 153
5.2.3.2
PIO Mode . ... ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 153
5.2.3.3
Bus Master Mode . ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 154
5.2.3.4
UltraDMA/33 Mode ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 155
5.2.4
Universal Serial Bus . ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 156
5.2.5
Sub-ISA Bus Interface .. .... ... ... ... ... .... ... ... ... .... ... ... ... ... 156
5.2.5.1
Sub-ISA Bus Cycles .. ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 157
5.2.5.2
Sub-ISA SupportofDelayed PCI Transactions . . . . ... ... ... ... .. ... ... .. 157
5.2.5.3
Sub-ISA Bus Data Steering ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 158
5.2.5.4
I/O Recovery Delays .. ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 158
5.2.5.5
ISA DMA . . ... ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 159
5.2.5.6
ROM Interface . ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 160
5.2.5.7
PCI and Sub-ISA Signal Cycle Multiplexing . ... .. ... ... ... ... .. ... ... .. 160


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