EFR32FG1V132F32GM48-B0 datasheet(6/101 Pages) SILABS

Part #	EFR32FG1V132F32GM48-B0

Description	EFR32FG1 Flex Gecko Proprietary Protocol SoC Family Data Sheet

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Manufacturer	SILABS [Silicon Laboratories]

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3.2.7 Flexible Frame Handling

EFR32FG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.

The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-

tor:

• Highly adjustable preamble length

• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts

• Frame disassembly and address matching (filtering) to accept or reject frames

• Automatic ACK frame assembly and transmission

• Fully flexible CRC generation and verification:

• Multiple CRC values can be embedded in a single frame

• 8, 16, 24 or 32-bit CRC value

• Configurable CRC bit and byte ordering

• Selectable bit-ordering (least significant or most significant bit first)

• Optional data whitening

• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding

• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing

• Optional symbol interleaving, typically used in combination with FEC

• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware

• UART encoding over air, with start and stop bit insertion / removal

• Test mode support, such as modulated or unmodulated carrier output

• Received frame timestamping

3.2.8 Packet and State Trace

The EFR32FG1 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It

features:

• Non-intrusive trace of transmit data, receive data and state information

• Data observability on a single-pin UART data output, or on a two-pin SPI data output

• Configurable data output bitrate / baudrate

• Multiplexed transmitted data, received data and state / meta information in a single serial data stream

3.2.9 Data Buffering

The EFR32FG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.

3.2.10 Radio Controller (RAC)

The Radio Controller controls the top level state of the radio subsystem in the EFR32FG1. It performs the following tasks:

• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry

• Run-time calibration of receiver, transmitter and frequency synthesizer

• Detailed frame transmission timing, including optional LBT or CSMA-CA

3.2.11 Random Number Generator

The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.

The data is suitable for use in cryptographic applications.

Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-

ber generator algorithms such as Fortuna.

EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet

System Overview

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Preliminary Rev. 0.9 | 5

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EFR32FG1V132F32GM48-B0 Datasheet(PDF) 6 Page - Silicon Laboratories

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