TB3R1, TB3R2

SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

PART NUMBER

PART MARKING

Package

LEAD FIISH

STATUS

TB3R1D

TB3R1

SOIC

NiPdAu

Production

TB3R2D

TB3R2

SOIC

NiPdAu

Production

POWER DISSIPATION RATINGS

THERMAL RESISTANCE,

DERATING

CIRCUIT BOARD

POWER RATING

POWER RATING

PACKAGE

JUNCTION-TO-AMBIENT

MODEL

WITH NO AIR FLOW

763 mW

131.1°C/W

7.6 mW/°C

305 mW

D

1190 mW

84.1°C/W

11.9 mW/°C

475 mW

831 mW

120.3°C/W

8.3 mW/°C

332 mW

DW

1240 mW

80.8°C/W

12.4 mW/°C

494 mW

(1)

In accordance with the low-K thermal metric definitions of EIA/JESD51-3.

(2)

In accordance with the high-K thermal metric definitions of EIA/JESD51-7.

THERMAL CHARACTERISTICs

PARAMETER

PACKAGE

VALUE

UNIT

D

47.5

°C/W

Junction-to-Board Thermal Resistance

DW

53.7

°C/W

D

44.2

°C/W

Junction-to-Case Thermal Resistance

DW

47.1

°C/W

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNIT

0 V to 6 V

6.5 V

All pins

±3 kV

ESD

All pins

±2 kV

Continuous power dissipation

See Dissipation Rating Table

-65°C to 150°C

(1)

Stresses beyond those listed under„ absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under„ recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Tested in accordance with JEDEC Standard 22, Test Method A114-A.

(3)

Tested in accordance with JEDEC Standard 22, Test Method C101.

2

Submit Documentation Feedback

Copyright © 2003–2008, Texas Instruments Incorporated

Product Folder Links: TB3R1 TB3R2