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TLV320AIC3104 Datasheet(PDF) 10 Page - Texas Instruments |
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TLV320AIC3104 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 97 page  10 TLV320AIC3104 SLAS510F – FEBRUARY 2007 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: TLV320AIC3104 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Electrical Characteristics (continued) At 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (5) When IOVDD < 1.6 V, minimum VIH is 1.1 V. (6) Additional power is consumed when the PLL is powered. Power supply rejection ratio 217 Hz, 100 mVpp on AVDD, DRVDD1/2 48 dB Mute attenuation 1-kHz output 107 dB DIGITAL I/O VIL Input low level –0.3 0.3 IOVDD V VIH Input high level (5) IOVDD > 1.6 V 0.7 IOVDD V IOVDD ≤ 1.6 V 1.1 VOL Output low level 0.1 IOVDD V VOH Output high level 0.8 IOVDD V CURRENT CONSUMPTION – DRVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V IIN IDRVDD + IAVDD RESET held low 0.1 μA IDVDD 0.2 IDRVDD + IAVDD Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal 2.15 mA IDVDD 0.48 IDRVDD + IAVDD Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal 4.1 IDVDD 0.62 IDRVDD + IAVDD Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal 4.31(6) IDVDD 2.45(6) IDRVDD + IAVDD Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 ksps, I2S slave 3.5 IDVDD 2.3 IDRVDD + IAVDD Stereo DAC playback to lineout, fS = 48 ksps, I2S slave, no signal 4.9 IDVDD 2.3 IDRVDD + IAVDD Stereo DAC playback to stereo single-ended headphone, fS = 48 ksps, I2S slave, no signal 6.7 IDVDD 2.3 IDRVDD + IAVDD Stereo line in to stereo line out, no signal 3.11 IDVDD 0 IDRVDD + IAVDD Extra power when PLL enabled 1.4 IDVDD 0.9 IDRVDD + IAVDD All blocks powered down. Headset detection enabled, headset not inserted 28 μA IDVDD 2 (1) All timing specifications are measured at characterization but not tested at final test. (2) All specifications at 25°C, DVDD = 1.8 V. 8.7 Audio Data Serial Interface Timing Requirements (1) (2) IOVDD = 1.1 V IOVDD = 3.3 V UNIT MIN MAX MIN MAX I2S/LJF/RJF TIMING IN MASTER MODE (See Figure 1) td(WS) ADWS/WCLK delay time 50 15 ns td(DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns |
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