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TLV320AIC3206 Datasheet(PDF) 9 Page - Texas Instruments |
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TLV320AIC3206 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 51 page  TLV320AIC3206 www.ti.com SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014 Electrical Characteristics, ADC (continued) At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DR Dynamic range A-weighted(1) (2) –60dB full-scale, 1kHz input signal 90 dB THD+N Total Harmonic Distortion plus –3dB full-scale, 1kHz input signal –81 dB Noise AUDIO ADC (Gain = 40dB) Input signal level (for 0dB output) Differential Input, CM = 0.9V, Channel Gain = 40dB 10 mVRMS 1kHz sine wave input Differential configuration IN1_L and IN1_R routed to Right ADC IN2_L and IN2_R routed to Left ADC Device Setup RIN = 10kΩ, fS = 48kHz, AOSR = 128 MCLK = 256 * fS PLL Disabled AGC = OFF Processing Block = PRB_R1, Power Tune = PTM_R4 ICN Idle-Channel Noise, A- Inputs ac-shorted to ground, input referred noise 2.8 μVRMS weighted(1) (2) AUDIO ADC 1kHz sine wave input 0.1 dB Single-ended configuration RIN = 20kΩ, fS = 48kHz, AOSR = 128, Gain Error MCLK = 256 * fS, PLL Disabled AGC = OFF, Channel Gain = 0dB Processing Block = PRB_R1, Power Tune = PTM_R4, CM = 0.9V 1kHz sine wave input at -3dBFS 109 dB Single-ended configuration IN1_L routed to Left ADC Input Channel Separation IN1_R routed to Right ADC, RIN = 20kΩ AGC = OFF, AOSR = 128, Channel Gain = 0dB, CM = 0.9V 1kHz sine wave input at –3dBFS on IN2_L, IN2_L 108 dB internally not routed. Input Pin Crosstalk IN1_L routed to Left ADC ac-coupled to ground 1kHz sine wave input at –3dBFS on IN2_R, IN2_R internally not routed. IN1_R routed to Right ADC ac-coupled to ground Single-ended configuration RIN = 20kΩ, AOSR = 128 Channel, Gain = 0dB, CM = 0.9V 217Hz, 100mVpp signal on AVdd, 55 dB PSRR Single-ended configuration, RIN= 20kΩ, Channel Gain = 0dB; CM = 0.9V Single-Ended, RIN = 10kΩ, PGA gain set to 0dB 0 dB Single-Ended, RIN = 10kΩ, PGA gain set to 47.5dB 47.5 dB Single-Ended, RIN = 20kΩ, PGA gain set to 0dB –6 dB ADC programmable gain amplifier gain Single-Ended, RIN = 20kΩ, PGA gain set to 47.5dB 41.5 dB Single-Ended, RIN = 40kΩ, PGA gain set to 0dB –12 dB Single-Ended, RIN = 40kΩ, PGA gain set to 47.5dB 35.5 dB ADC programmable gain 1kHz tone 0.5 dB amplifier step size Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TLV320AIC3206 |
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